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448 lines
14 KiB
448 lines
14 KiB
/*
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* Description of Z8530 Z85C30 and Z85230 communications chips
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1998 Alan Cox <alan@lxorguk.ukuu.org.uk>
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*/
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#ifndef _Z8530_H
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#define _Z8530_H
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#include <linux/tty.h>
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#include <linux/interrupt.h>
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/* Conversion routines to/from brg time constants from/to bits
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* per second.
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*/
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#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
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#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
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/* The Zilog register set */
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#define FLAG 0x7e
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/* Write Register 0 */
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#define R0 0 /* Register selects */
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#define R1 1
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#define R2 2
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#define R3 3
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#define R4 4
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#define R5 5
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#define R6 6
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#define R7 7
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#define R8 8
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#define R9 9
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#define R10 10
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#define R11 11
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#define R12 12
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#define R13 13
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#define R14 14
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#define R15 15
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#define RPRIME 16 /* Indicate a prime register access on 230 */
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#define NULLCODE 0 /* Null Code */
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#define POINT_HIGH 0x8 /* Select upper half of registers */
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#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
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#define SEND_ABORT 0x18 /* HDLC Abort */
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#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
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#define RES_Tx_P 0x28 /* Reset TxINT Pending */
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#define ERR_RES 0x30 /* Error Reset */
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#define RES_H_IUS 0x38 /* Reset highest IUS */
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#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
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#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
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#define RES_EOM_L 0xC0 /* Reset EOM latch */
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/* Write Register 1 */
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#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
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#define TxINT_ENAB 0x2 /* Tx Int Enable */
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#define PAR_SPEC 0x4 /* Parity is special condition */
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#define RxINT_DISAB 0 /* Rx Int Disable */
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#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
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#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
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#define INT_ERR_Rx 0x18 /* Int on error only */
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#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
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#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
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#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
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/* Write Register #2 (Interrupt Vector) */
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/* Write Register 3 */
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#define RxENABLE 0x1 /* Rx Enable */
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#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
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#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
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#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
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#define ENT_HM 0x10 /* Enter Hunt Mode */
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#define AUTO_ENAB 0x20 /* Auto Enables */
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#define Rx5 0x0 /* Rx 5 Bits/Character */
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#define Rx7 0x40 /* Rx 7 Bits/Character */
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#define Rx6 0x80 /* Rx 6 Bits/Character */
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#define Rx8 0xc0 /* Rx 8 Bits/Character */
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/* Write Register 4 */
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#define PAR_ENA 0x1 /* Parity Enable */
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#define PAR_EVEN 0x2 /* Parity Even/Odd* */
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#define SYNC_ENAB 0 /* Sync Modes Enable */
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#define SB1 0x4 /* 1 stop bit/char */
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#define SB15 0x8 /* 1.5 stop bits/char */
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#define SB2 0xc /* 2 stop bits/char */
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#define MONSYNC 0 /* 8 Bit Sync character */
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#define BISYNC 0x10 /* 16 bit sync character */
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#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
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#define EXTSYNC 0x30 /* External Sync Mode */
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#define X1CLK 0x0 /* x1 clock mode */
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#define X16CLK 0x40 /* x16 clock mode */
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#define X32CLK 0x80 /* x32 clock mode */
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#define X64CLK 0xC0 /* x64 clock mode */
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/* Write Register 5 */
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#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
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#define RTS 0x2 /* RTS */
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#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
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#define TxENAB 0x8 /* Tx Enable */
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#define SND_BRK 0x10 /* Send Break */
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#define Tx5 0x0 /* Tx 5 bits (or less)/character */
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#define Tx7 0x20 /* Tx 7 bits/character */
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#define Tx6 0x40 /* Tx 6 bits/character */
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#define Tx8 0x60 /* Tx 8 bits/character */
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#define DTR 0x80 /* DTR */
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/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
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/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
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/* Write Register 8 (transmit buffer) */
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/* Write Register 9 (Master interrupt control) */
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#define VIS 1 /* Vector Includes Status */
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#define NV 2 /* No Vector */
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#define DLC 4 /* Disable Lower Chain */
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#define MIE 8 /* Master Interrupt Enable */
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#define STATHI 0x10 /* Status high */
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#define NORESET 0 /* No reset on write to R9 */
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#define CHRB 0x40 /* Reset channel B */
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#define CHRA 0x80 /* Reset channel A */
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#define FHWRES 0xc0 /* Force hardware reset */
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/* Write Register 10 (misc control bits) */
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#define BIT6 1 /* 6 bit/8bit sync */
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#define LOOPMODE 2 /* SDLC Loop mode */
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#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
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#define MARKIDLE 8 /* Mark/flag on idle */
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#define GAOP 0x10 /* Go active on poll */
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#define NRZ 0 /* NRZ mode */
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#define NRZI 0x20 /* NRZI mode */
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#define FM1 0x40 /* FM1 (transition = 1) */
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#define FM0 0x60 /* FM0 (transition = 0) */
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#define CRCPS 0x80 /* CRC Preset I/O */
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/* Write Register 11 (Clock Mode control) */
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#define TRxCXT 0 /* TRxC = Xtal output */
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#define TRxCTC 1 /* TRxC = Transmit clock */
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#define TRxCBR 2 /* TRxC = BR Generator Output */
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#define TRxCDP 3 /* TRxC = DPLL output */
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#define TRxCOI 4 /* TRxC O/I */
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#define TCRTxCP 0 /* Transmit clock = RTxC pin */
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#define TCTRxCP 8 /* Transmit clock = TRxC pin */
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#define TCBR 0x10 /* Transmit clock = BR Generator output */
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#define TCDPLL 0x18 /* Transmit clock = DPLL output */
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#define RCRTxCP 0 /* Receive clock = RTxC pin */
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#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
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#define RCBR 0x40 /* Receive clock = BR Generator output */
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#define RCDPLL 0x60 /* Receive clock = DPLL output */
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#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
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/* Write Register 12 (lower byte of baud rate generator time constant) */
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/* Write Register 13 (upper byte of baud rate generator time constant) */
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/* Write Register 14 (Misc control bits) */
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#define BRENABL 1 /* Baud rate generator enable */
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#define BRSRC 2 /* Baud rate generator source */
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#define DTRREQ 4 /* DTR/Request function */
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#define AUTOECHO 8 /* Auto Echo */
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#define LOOPBAK 0x10 /* Local loopback */
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#define SEARCH 0x20 /* Enter search mode */
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#define RMC 0x40 /* Reset missing clock */
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#define DISDPLL 0x60 /* Disable DPLL */
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#define SSBR 0x80 /* Set DPLL source = BR generator */
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#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
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#define SFMM 0xc0 /* Set FM mode */
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#define SNRZI 0xe0 /* Set NRZI mode */
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/* Write Register 15 (external/status interrupt control) */
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#define PRIME 1 /* R5' etc register access (Z85C30/230 only) */
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#define ZCIE 2 /* Zero count IE */
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#define FIFOE 4 /* Z85230 only */
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#define DCDIE 8 /* DCD IE */
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#define SYNCIE 0x10 /* Sync/hunt IE */
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#define CTSIE 0x20 /* CTS IE */
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#define TxUIE 0x40 /* Tx Underrun/EOM IE */
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#define BRKIE 0x80 /* Break/Abort IE */
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/* Read Register 0 */
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#define Rx_CH_AV 0x1 /* Rx Character Available */
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#define ZCOUNT 0x2 /* Zero count */
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#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
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#define DCD 0x8 /* DCD */
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#define SYNC_HUNT 0x10 /* Sync/hunt */
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#define CTS 0x20 /* CTS */
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#define TxEOM 0x40 /* Tx underrun */
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#define BRK_ABRT 0x80 /* Break/Abort */
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/* Read Register 1 */
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#define ALL_SNT 0x1 /* All sent */
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/* Residue Data for 8 Rx bits/char programmed */
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#define RES3 0x8 /* 0/3 */
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#define RES4 0x4 /* 0/4 */
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#define RES5 0xc /* 0/5 */
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#define RES6 0x2 /* 0/6 */
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#define RES7 0xa /* 0/7 */
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#define RES8 0x6 /* 0/8 */
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#define RES18 0xe /* 1/8 */
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#define RES28 0x0 /* 2/8 */
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/* Special Rx Condition Interrupts */
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#define PAR_ERR 0x10 /* Parity error */
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#define Rx_OVR 0x20 /* Rx Overrun Error */
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#define CRC_ERR 0x40 /* CRC/Framing Error */
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#define END_FR 0x80 /* End of Frame (SDLC) */
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/* Read Register 2 (channel b only) - Interrupt vector */
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/* Read Register 3 (interrupt pending register) ch a only */
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#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
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#define CHBTxIP 0x2 /* Channel B Tx IP */
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#define CHBRxIP 0x4 /* Channel B Rx IP */
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#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
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#define CHATxIP 0x10 /* Channel A Tx IP */
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#define CHARxIP 0x20 /* Channel A Rx IP */
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/* Read Register 8 (receive data register) */
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/* Read Register 10 (misc status bits) */
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#define ONLOOP 2 /* On loop */
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#define LOOPSEND 0x10 /* Loop sending */
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#define CLK2MIS 0x40 /* Two clocks missing */
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#define CLK1MIS 0x80 /* One clock missing */
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/* Read Register 12 (lower byte of baud rate generator constant) */
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/* Read Register 13 (upper byte of baud rate generator constant) */
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/* Read Register 15 (value of WR 15) */
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/*
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* Interrupt handling functions for this SCC
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*/
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struct z8530_channel;
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struct z8530_irqhandler
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{
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void (*rx)(struct z8530_channel *);
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void (*tx)(struct z8530_channel *);
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void (*status)(struct z8530_channel *);
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};
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/*
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* A channel of the Z8530
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*/
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struct z8530_channel
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{
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struct z8530_irqhandler *irqs; /* IRQ handlers */
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/*
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* Synchronous
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*/
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u16 count; /* Buyes received */
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u16 max; /* Most we can receive this frame */
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u16 mtu; /* MTU of the device */
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u8 *dptr; /* Pointer into rx buffer */
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struct sk_buff *skb; /* Buffer dptr points into */
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struct sk_buff *skb2; /* Pending buffer */
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u8 status; /* Current DCD */
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u8 dcdcheck; /* which bit to check for line */
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u8 sync; /* Set if in sync mode */
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u8 regs[32]; /* Register map for the chip */
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u8 pendregs[32]; /* Pending register values */
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struct sk_buff *tx_skb; /* Buffer being transmitted */
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struct sk_buff *tx_next_skb; /* Next transmit buffer */
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u8 *tx_ptr; /* Byte pointer into the buffer */
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u8 *tx_next_ptr; /* Next pointer to use */
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u8 *tx_dma_buf[2]; /* TX flip buffers for DMA */
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u8 tx_dma_used; /* Flip buffer usage toggler */
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u16 txcount; /* Count of bytes to transmit */
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void (*rx_function)(struct z8530_channel *, struct sk_buff *);
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/*
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* Sync DMA
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*/
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u8 rxdma; /* DMA channels */
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u8 txdma;
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u8 rxdma_on; /* DMA active if flag set */
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u8 txdma_on;
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u8 dma_num; /* Buffer we are DMAing into */
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u8 dma_ready; /* Is the other buffer free */
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u8 dma_tx; /* TX is to use DMA */
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u8 *rx_buf[2]; /* The flip buffers */
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/*
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* System
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*/
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struct z8530_dev *dev; /* Z85230 chip instance we are from */
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unsigned long ctrlio; /* I/O ports */
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unsigned long dataio;
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/*
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* For PC we encode this way.
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*/
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#define Z8530_PORT_SLEEP 0x80000000
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#define Z8530_PORT_OF(x) ((x)&0xFFFF)
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u32 rx_overrun; /* Overruns - not done yet */
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u32 rx_crc_err;
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/*
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* Bound device pointers
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*/
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void *private; /* For our owner */
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struct net_device *netdevice; /* Network layer device */
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/*
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* Async features
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*/
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struct tty_struct *tty; /* Attached terminal */
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int line; /* Minor number */
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wait_queue_head_t open_wait; /* Tasks waiting to open */
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wait_queue_head_t close_wait; /* and for close to end */
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unsigned long event; /* Pending events */
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int fdcount; /* # of fd on device */
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int blocked_open; /* # of blocked opens */
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int x_char; /* XON/XOF char */
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unsigned char *xmit_buf; /* Transmit pointer */
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int xmit_head; /* Transmit ring */
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int xmit_tail;
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int xmit_cnt;
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int flags;
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int timeout;
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int xmit_fifo_size; /* Transmit FIFO info */
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int close_delay; /* Do we wait for drain on close ? */
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unsigned short closing_wait;
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/* We need to know the current clock divisor
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* to read the bps rate the chip has currently
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* loaded.
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*/
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unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */
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int zs_baud;
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int magic;
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int baud_base; /* Baud parameters */
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int custom_divisor;
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unsigned char tx_active; /* character is being xmitted */
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unsigned char tx_stopped; /* output is suspended */
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spinlock_t *lock; /* Device lock */
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};
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/*
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* Each Z853x0 device.
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*/
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struct z8530_dev
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{
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char *name; /* Device instance name */
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struct z8530_channel chanA; /* SCC channel A */
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struct z8530_channel chanB; /* SCC channel B */
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int type;
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#define Z8530 0 /* NMOS dinosaur */
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#define Z85C30 1 /* CMOS - better */
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#define Z85230 2 /* CMOS with real FIFO */
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int irq; /* Interrupt for the device */
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int active; /* Soft interrupt enable - the Mac doesn't
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always have a hard disable on its 8530s... */
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spinlock_t lock;
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};
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/*
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* Functions
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*/
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extern u8 z8530_dead_port[];
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extern u8 z8530_hdlc_kilostream_85230[];
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extern u8 z8530_hdlc_kilostream[];
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extern irqreturn_t z8530_interrupt(int, void *);
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extern void z8530_describe(struct z8530_dev *, char *mapping, unsigned long io);
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extern int z8530_init(struct z8530_dev *);
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extern int z8530_shutdown(struct z8530_dev *);
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extern int z8530_sync_open(struct net_device *, struct z8530_channel *);
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extern int z8530_sync_close(struct net_device *, struct z8530_channel *);
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extern int z8530_sync_dma_open(struct net_device *, struct z8530_channel *);
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extern int z8530_sync_dma_close(struct net_device *, struct z8530_channel *);
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extern int z8530_sync_txdma_open(struct net_device *, struct z8530_channel *);
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extern int z8530_sync_txdma_close(struct net_device *, struct z8530_channel *);
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extern int z8530_channel_load(struct z8530_channel *, u8 *);
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extern netdev_tx_t z8530_queue_xmit(struct z8530_channel *c,
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struct sk_buff *skb);
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extern void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb);
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/*
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* Standard interrupt vector sets
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*/
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extern struct z8530_irqhandler z8530_sync, z8530_async, z8530_nop;
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/*
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* Asynchronous Interfacing
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*/
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#define SERIAL_MAGIC 0x5301
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/*
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* The size of the serial xmit buffer is 1 page, or 4096 bytes
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*/
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#define SERIAL_XMIT_SIZE 4096
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#define WAKEUP_CHARS 256
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/*
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* Events are used to schedule things to happen at timer-interrupt
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* time, instead of at rs interrupt time.
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*/
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#define RS_EVENT_WRITE_WAKEUP 0
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/* Internal flags used only by kernel/chr_drv/serial.c */
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#define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */
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#define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */
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#define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
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#define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
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#define ZILOG_CLOSING 0x08000000 /* Serial port is closing */
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#define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */
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#define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */
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#endif /* !(_Z8530_H) */
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