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279 lines
6.9 KiB
279 lines
6.9 KiB
/*
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* arch/score/mm/cache.c
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*
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* Score Processor version.
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*
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* Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
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* Lennox Wu <lennox.wu@sunplusct.com>
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* Chen Liqin <liqin.chen@sunplusct.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/fs.h>
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#include <asm/mmu_context.h>
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/*
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Just flush entire Dcache!!
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You must ensure the page doesn't include instructions, because
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the function will not flush the Icache.
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The addr must be cache aligned.
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*/
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static void flush_data_cache_page(unsigned long addr)
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{
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unsigned int i;
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for (i = 0; i < (PAGE_SIZE / L1_CACHE_BYTES); i += L1_CACHE_BYTES) {
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__asm__ __volatile__(
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"cache 0x0e, [%0, 0]\n"
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"cache 0x1a, [%0, 0]\n"
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"nop\n"
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: : "r" (addr));
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addr += L1_CACHE_BYTES;
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}
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}
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping = page_mapping(page);
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unsigned long addr;
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if (PageHighMem(page))
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return;
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if (mapping && !mapping_mapped(mapping)) {
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set_bit(PG_dcache_dirty, &(page)->flags);
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return;
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}
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/*
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* We could delay the flush for the !page_mapping case too. But that
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* case is for exec env/arg pages and those are %99 certainly going to
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* get faulted into the tlb (and thus flushed) anyways.
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*/
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addr = (unsigned long) page_address(page);
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flush_data_cache_page(addr);
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}
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/* called by update_mmu_cache. */
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void __update_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t pte)
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{
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struct page *page;
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unsigned long pfn, addr;
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int exec = (vma->vm_flags & VM_EXEC);
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pfn = pte_pfn(pte);
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if (unlikely(!pfn_valid(pfn)))
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return;
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page = pfn_to_page(pfn);
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if (page_mapping(page) && test_bit(PG_dcache_dirty, &(page)->flags)) {
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addr = (unsigned long) page_address(page);
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if (exec)
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flush_data_cache_page(addr);
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clear_bit(PG_dcache_dirty, &(page)->flags);
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}
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}
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static inline void setup_protection_map(void)
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{
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protection_map[0] = PAGE_NONE;
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protection_map[1] = PAGE_READONLY;
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protection_map[2] = PAGE_COPY;
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protection_map[3] = PAGE_COPY;
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protection_map[4] = PAGE_READONLY;
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protection_map[5] = PAGE_READONLY;
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protection_map[6] = PAGE_COPY;
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protection_map[7] = PAGE_COPY;
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protection_map[8] = PAGE_NONE;
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protection_map[9] = PAGE_READONLY;
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protection_map[10] = PAGE_SHARED;
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protection_map[11] = PAGE_SHARED;
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protection_map[12] = PAGE_READONLY;
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protection_map[13] = PAGE_READONLY;
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protection_map[14] = PAGE_SHARED;
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protection_map[15] = PAGE_SHARED;
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}
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void __devinit cpu_cache_init(void)
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{
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setup_protection_map();
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}
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void flush_icache_all(void)
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{
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__asm__ __volatile__(
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"la r8, flush_icache_all\n"
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"cache 0x10, [r8, 0]\n"
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"nop\nnop\nnop\nnop\nnop\nnop\n"
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: : : "r8");
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}
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void flush_dcache_all(void)
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{
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__asm__ __volatile__(
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"la r8, flush_dcache_all\n"
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"cache 0x1f, [r8, 0]\n"
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"nop\nnop\nnop\nnop\nnop\nnop\n"
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"cache 0x1a, [r8, 0]\n"
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"nop\nnop\nnop\nnop\nnop\nnop\n"
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: : : "r8");
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}
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void flush_cache_all(void)
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{
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__asm__ __volatile__(
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"la r8, flush_cache_all\n"
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"cache 0x10, [r8, 0]\n"
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"nop\nnop\nnop\nnop\nnop\nnop\n"
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"cache 0x1f, [r8, 0]\n"
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"nop\nnop\nnop\nnop\nnop\nnop\n"
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"cache 0x1a, [r8, 0]\n"
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"nop\nnop\nnop\nnop\nnop\nnop\n"
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: : : "r8");
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}
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void flush_cache_mm(struct mm_struct *mm)
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{
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if (!(mm->context))
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return;
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flush_cache_all();
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}
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/*if we flush a range precisely , the processing may be very long.
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We must check each page in the range whether present. If the page is present,
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we can flush the range in the page. Be careful, the range may be cross two
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page, a page is present and another is not present.
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*/
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/*
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The interface is provided in hopes that the port can find
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a suitably efficient method for removing multiple page
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sized regions from the cache.
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*/
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void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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int exec = vma->vm_flags & VM_EXEC;
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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if (!(mm->context))
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return;
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pgdp = pgd_offset(mm, start);
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pudp = pud_offset(pgdp, start);
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pmdp = pmd_offset(pudp, start);
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ptep = pte_offset(pmdp, start);
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while (start <= end) {
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unsigned long tmpend;
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pgdp = pgd_offset(mm, start);
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pudp = pud_offset(pgdp, start);
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pmdp = pmd_offset(pudp, start);
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ptep = pte_offset(pmdp, start);
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if (!(pte_val(*ptep) & _PAGE_PRESENT)) {
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start = (start + PAGE_SIZE) & ~(PAGE_SIZE - 1);
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continue;
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}
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tmpend = (start | (PAGE_SIZE-1)) > end ?
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end : (start | (PAGE_SIZE-1));
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flush_dcache_range(start, tmpend);
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if (exec)
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flush_icache_range(start, tmpend);
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start = (start + PAGE_SIZE) & ~(PAGE_SIZE - 1);
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}
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}
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void flush_cache_page(struct vm_area_struct *vma,
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unsigned long addr, unsigned long pfn)
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{
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int exec = vma->vm_flags & VM_EXEC;
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unsigned long kaddr = 0xa0000000 | (pfn << PAGE_SHIFT);
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flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
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if (exec)
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flush_icache_range(kaddr, kaddr + PAGE_SIZE);
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}
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void flush_cache_sigtramp(unsigned long addr)
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{
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__asm__ __volatile__(
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"cache 0x02, [%0, 0]\n"
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"nop\nnop\nnop\nnop\nnop\n"
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"cache 0x02, [%0, 0x4]\n"
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"nop\nnop\nnop\nnop\nnop\n"
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"cache 0x0d, [%0, 0]\n"
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"nop\nnop\nnop\nnop\nnop\n"
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"cache 0x0d, [%0, 0x4]\n"
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"nop\nnop\nnop\nnop\nnop\n"
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"cache 0x1a, [%0, 0]\n"
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"nop\nnop\nnop\nnop\nnop\n"
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: : "r" (addr));
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}
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/*
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1. WB and invalid a cache line of Dcache
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2. Drain Write Buffer
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the range must be smaller than PAGE_SIZE
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*/
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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int size, i;
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start = start & ~(L1_CACHE_BYTES - 1);
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end = end & ~(L1_CACHE_BYTES - 1);
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size = end - start;
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/* flush dcache to ram, and invalidate dcache lines. */
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for (i = 0; i < size; i += L1_CACHE_BYTES) {
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__asm__ __volatile__(
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"cache 0x0e, [%0, 0]\n"
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"nop\nnop\nnop\nnop\nnop\n"
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"cache 0x1a, [%0, 0]\n"
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"nop\nnop\nnop\nnop\nnop\n"
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: : "r" (start));
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start += L1_CACHE_BYTES;
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}
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}
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void flush_icache_range(unsigned long start, unsigned long end)
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{
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int size, i;
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start = start & ~(L1_CACHE_BYTES - 1);
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end = end & ~(L1_CACHE_BYTES - 1);
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size = end - start;
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/* invalidate icache lines. */
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for (i = 0; i < size; i += L1_CACHE_BYTES) {
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__asm__ __volatile__(
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"cache 0x02, [%0, 0]\n"
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"nop\nnop\nnop\nnop\nnop\n"
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: : "r" (start));
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start += L1_CACHE_BYTES;
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}
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}
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