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507 lines
12 KiB
507 lines
12 KiB
/*
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* arch/arm/mach-ixp4xx/common-pci.c
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*
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* IXP4XX PCI routines for all platforms
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*
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* Maintainer: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright (C) 2002 Intel Corporation.
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* Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com>
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* Copyright (C) 2003-2004 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <asm/dma-mapping.h>
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#include <asm/cputype.h>
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#include <asm/irq.h>
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#include <asm/sizes.h>
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#include <asm/system.h>
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#include <asm/mach/pci.h>
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#include <mach/hardware.h>
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/*
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* IXP4xx PCI read function is dependent on whether we are
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* running A0 or B0 (AppleGate) silicon.
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*/
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int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
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/*
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* Base address for PCI regsiter region
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*/
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unsigned long ixp4xx_pci_reg_base = 0;
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/*
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* PCI cfg an I/O routines are done by programming a
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* command/byte enable register, and then read/writing
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* the data from a data regsiter. We need to ensure
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* these transactions are atomic or we will end up
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* with corrupt data on the bus or in a driver.
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*/
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static DEFINE_SPINLOCK(ixp4xx_pci_lock);
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/*
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* Read from PCI config space
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*/
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static void crp_read(u32 ad_cbe, u32 *data)
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{
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unsigned long flags;
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spin_lock_irqsave(&ixp4xx_pci_lock, flags);
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*PCI_CRP_AD_CBE = ad_cbe;
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*data = *PCI_CRP_RDATA;
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spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
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}
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/*
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* Write to PCI config space
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*/
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static void crp_write(u32 ad_cbe, u32 data)
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{
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unsigned long flags;
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spin_lock_irqsave(&ixp4xx_pci_lock, flags);
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*PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe;
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*PCI_CRP_WDATA = data;
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spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
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}
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static inline int check_master_abort(void)
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{
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/* check Master Abort bit after access */
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unsigned long isr = *PCI_ISR;
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if (isr & PCI_ISR_PFE) {
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/* make sure the Master Abort bit is reset */
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*PCI_ISR = PCI_ISR_PFE;
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pr_debug("%s failed\n", __func__);
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return 1;
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}
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return 0;
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}
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int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data)
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{
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unsigned long flags;
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int retval = 0;
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int i;
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spin_lock_irqsave(&ixp4xx_pci_lock, flags);
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*PCI_NP_AD = addr;
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/*
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* PCI workaround - only works if NP PCI space reads have
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* no side effects!!! Read 8 times. last one will be good.
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*/
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for (i = 0; i < 8; i++) {
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*PCI_NP_CBE = cmd;
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*data = *PCI_NP_RDATA;
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*data = *PCI_NP_RDATA;
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}
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if(check_master_abort())
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retval = 1;
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spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
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return retval;
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}
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int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data)
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{
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unsigned long flags;
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int retval = 0;
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spin_lock_irqsave(&ixp4xx_pci_lock, flags);
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*PCI_NP_AD = addr;
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/* set up and execute the read */
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*PCI_NP_CBE = cmd;
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/* the result of the read is now in NP_RDATA */
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*data = *PCI_NP_RDATA;
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if(check_master_abort())
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retval = 1;
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spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
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return retval;
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}
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int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data)
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{
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unsigned long flags;
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int retval = 0;
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spin_lock_irqsave(&ixp4xx_pci_lock, flags);
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*PCI_NP_AD = addr;
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/* set up the write */
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*PCI_NP_CBE = cmd;
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/* execute the write by writing to NP_WDATA */
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*PCI_NP_WDATA = data;
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if(check_master_abort())
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retval = 1;
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spin_unlock_irqrestore(&ixp4xx_pci_lock, flags);
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return retval;
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}
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static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where)
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{
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u32 addr;
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if (!bus_num) {
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/* type 0 */
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addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) |
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(where & ~3);
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} else {
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/* type 1 */
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addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) |
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((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1;
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}
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return addr;
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}
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/*
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* Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
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* 0 and 3 are not valid indexes...
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*/
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static u32 bytemask[] = {
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/*0*/ 0,
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/*1*/ 0xff,
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/*2*/ 0xffff,
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/*3*/ 0,
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/*4*/ 0xffffffff,
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};
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static u32 local_byte_lane_enable_bits(u32 n, int size)
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{
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if (size == 1)
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return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL;
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if (size == 2)
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return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL;
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if (size == 4)
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return 0;
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return 0xffffffff;
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}
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static int local_read_config(int where, int size, u32 *value)
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{
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u32 n, data;
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pr_debug("local_read_config from %d size %d\n", where, size);
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n = where % 4;
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crp_read(where & ~3, &data);
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*value = (data >> (8*n)) & bytemask[size];
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pr_debug("local_read_config read %#x\n", *value);
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return PCIBIOS_SUCCESSFUL;
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}
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static int local_write_config(int where, int size, u32 value)
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{
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u32 n, byte_enables, data;
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pr_debug("local_write_config %#x to %d size %d\n", value, where, size);
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n = where % 4;
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byte_enables = local_byte_lane_enable_bits(n, size);
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if (byte_enables == 0xffffffff)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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data = value << (8*n);
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crp_write((where & ~3) | byte_enables, data);
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return PCIBIOS_SUCCESSFUL;
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}
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static u32 byte_lane_enable_bits(u32 n, int size)
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{
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if (size == 1)
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return (0xf & ~BIT(n)) << 4;
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if (size == 2)
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return (0xf & ~(BIT(n) | BIT(n+1))) << 4;
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if (size == 4)
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return 0;
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return 0xffffffff;
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}
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static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
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{
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u32 n, byte_enables, addr, data;
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u8 bus_num = bus->number;
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pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
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bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
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*value = 0xffffffff;
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n = where % 4;
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byte_enables = byte_lane_enable_bits(n, size);
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if (byte_enables == 0xffffffff)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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addr = ixp4xx_config_addr(bus_num, devfn, where);
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if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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*value = (data >> (8*n)) & bytemask[size];
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pr_debug("read_config_byte read %#x\n", *value);
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return PCIBIOS_SUCCESSFUL;
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}
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static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
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{
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u32 n, byte_enables, addr, data;
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u8 bus_num = bus->number;
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pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
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size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
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n = where % 4;
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byte_enables = byte_lane_enable_bits(n, size);
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if (byte_enables == 0xffffffff)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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addr = ixp4xx_config_addr(bus_num, devfn, where);
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data = value << (8*n);
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if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops ixp4xx_ops = {
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.read = ixp4xx_pci_read_config,
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.write = ixp4xx_pci_write_config,
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};
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/*
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* PCI abort handler
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*/
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static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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{
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u32 isr, status;
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isr = *PCI_ISR;
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local_read_config(PCI_STATUS, 2, &status);
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pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, "
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"status = %#x\n", addr, isr, status);
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/* make sure the Master Abort bit is reset */
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*PCI_ISR = PCI_ISR_PFE;
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status |= PCI_STATUS_REC_MASTER_ABORT;
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local_write_config(PCI_STATUS, 2, status);
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/*
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* If it was an imprecise abort, then we need to correct the
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* return address to be _after_ the instruction.
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*/
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if (fsr & (1 << 10))
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regs->ARM_pc += 4;
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return 0;
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}
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/*
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* Setup DMA mask to 64MB on PCI devices. Ignore all other devices.
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*/
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static int ixp4xx_pci_platform_notify(struct device *dev)
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{
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if(dev->bus == &pci_bus_type) {
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*dev->dma_mask = SZ_64M - 1;
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dev->coherent_dma_mask = SZ_64M - 1;
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dmabounce_register_dev(dev, 2048, 4096);
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}
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return 0;
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}
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static int ixp4xx_pci_platform_notify_remove(struct device *dev)
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{
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if(dev->bus == &pci_bus_type) {
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dmabounce_unregister_dev(dev);
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}
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return 0;
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}
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int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
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}
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/*
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* Only first 64MB of memory can be accessed via PCI.
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* We use GFP_DMA to allocate safe buffers to do map/unmap.
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* This is really ugly and we need a better way of specifying
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* DMA-capable regions of memory.
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*/
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void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
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unsigned long *zhole_size)
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{
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unsigned int sz = SZ_64M >> PAGE_SHIFT;
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/*
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* Only adjust if > 64M on current system
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*/
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if (node || (zone_size[0] <= sz))
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return;
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zone_size[1] = zone_size[0] - sz;
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zone_size[0] = sz;
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zhole_size[1] = zhole_size[0];
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zhole_size[0] = 0;
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}
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void __init ixp4xx_pci_preinit(void)
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{
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unsigned long cpuid = read_cpuid_id();
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/*
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* Determine which PCI read method to use.
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* Rev 0 IXP425 requires workaround.
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*/
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if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
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printk("PCI: IXP42x A0 silicon detected - "
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"PCI Non-Prefetch Workaround Enabled\n");
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ixp4xx_pci_read = ixp4xx_pci_read_errata;
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} else
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ixp4xx_pci_read = ixp4xx_pci_read_no_errata;
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/* hook in our fault handler for PCI errors */
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hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort");
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pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
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/*
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* We use identity AHB->PCI address translation
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* in the 0x48000000 to 0x4bffffff address space
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*/
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*PCI_PCIMEMBASE = 0x48494A4B;
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/*
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* We also use identity PCI->AHB address translation
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* in 4 16MB BARs that begin at the physical memory start
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*/
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*PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
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((PHYS_OFFSET & 0xFF000000) >> 8) +
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((PHYS_OFFSET & 0xFF000000) >> 16) +
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((PHYS_OFFSET & 0xFF000000) >> 24) +
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0x00010203;
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if (*PCI_CSR & PCI_CSR_HOST) {
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printk("PCI: IXP4xx is host\n");
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pr_debug("setup BARs in controller\n");
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/*
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* We configure the PCI inbound memory windows to be
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* 1:1 mapped to SDRAM
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*/
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local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
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local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
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local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
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local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M);
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/*
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* Enable CSR window at 64 MiB to allow PCI masters
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* to continue prefetching past 64 MiB boundary.
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*/
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local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
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/*
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* Enable the IO window to be way up high, at 0xfffffc00
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*/
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local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
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} else {
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printk("PCI: IXP4xx is target - No bus scan performed\n");
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}
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printk("PCI: IXP4xx Using %s access for memory space\n",
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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"direct"
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#else
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"indirect"
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#endif
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);
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pr_debug("clear error bits in ISR\n");
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*PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
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/*
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* Set Initialize Complete in PCI Control Register: allow IXP4XX to
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* respond to PCI configuration cycles. Specify that the AHB bus is
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* operating in big endian mode. Set up byte lane swapping between
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* little-endian PCI and the big-endian AHB bus
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*/
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#ifdef __ARMEB__
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*PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
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#else
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*PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE;
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#endif
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pr_debug("DONE\n");
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}
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int ixp4xx_setup(int nr, struct pci_sys_data *sys)
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{
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struct resource *res;
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if (nr >= 1)
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return 0;
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res = kzalloc(sizeof(*res) * 2, GFP_KERNEL);
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if (res == NULL) {
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/*
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* If we're out of memory this early, something is wrong,
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* so we might as well catch it here.
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*/
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panic("PCI: unable to allocate resources?\n");
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}
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local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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res[0].name = "PCI I/O Space";
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res[0].start = 0x00000000;
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res[0].end = 0x0000ffff;
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res[0].flags = IORESOURCE_IO;
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res[1].name = "PCI Memory Space";
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res[1].start = PCIBIOS_MIN_MEM;
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res[1].end = PCIBIOS_MAX_MEM;
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res[1].flags = IORESOURCE_MEM;
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request_resource(&ioport_resource, &res[0]);
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request_resource(&iomem_resource, &res[1]);
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sys->resource[0] = &res[0];
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sys->resource[1] = &res[1];
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sys->resource[2] = NULL;
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platform_notify = ixp4xx_pci_platform_notify;
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platform_notify_remove = ixp4xx_pci_platform_notify_remove;
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return 1;
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}
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struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
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{
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return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
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}
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EXPORT_SYMBOL(ixp4xx_pci_read);
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EXPORT_SYMBOL(ixp4xx_pci_write);
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