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630 lines
18 KiB
630 lines
18 KiB
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <linux/swiotlb.h>
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#include <linux/vmalloc.h>
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#include <linux/export.h>
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#include <asm/tlbflush.h>
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#include <asm/homecache.h>
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/* Generic DMA mapping functions: */
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/*
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* Allocate what Linux calls "coherent" memory. On TILEPro this is
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* uncached memory; on TILE-Gx it is hash-for-home memory.
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*/
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#ifdef __tilepro__
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#define PAGE_HOME_DMA PAGE_HOME_UNCACHED
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#else
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#define PAGE_HOME_DMA PAGE_HOME_HASH
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#endif
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static void *tile_dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp,
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struct dma_attrs *attrs)
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{
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u64 dma_mask = (dev && dev->coherent_dma_mask) ?
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dev->coherent_dma_mask : DMA_BIT_MASK(32);
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int node = dev ? dev_to_node(dev) : 0;
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int order = get_order(size);
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struct page *pg;
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dma_addr_t addr;
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gfp |= __GFP_ZERO;
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/*
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* If the mask specifies that the memory be in the first 4 GB, then
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* we force the allocation to come from the DMA zone. We also
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* force the node to 0 since that's the only node where the DMA
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* zone isn't empty. If the mask size is smaller than 32 bits, we
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* may still not be able to guarantee a suitable memory address, in
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* which case we will return NULL. But such devices are uncommon.
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*/
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if (dma_mask <= DMA_BIT_MASK(32)) {
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gfp |= GFP_DMA;
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node = 0;
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}
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pg = homecache_alloc_pages_node(node, gfp, order, PAGE_HOME_DMA);
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if (pg == NULL)
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return NULL;
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addr = page_to_phys(pg);
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if (addr + size > dma_mask) {
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__homecache_free_pages(pg, order);
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return NULL;
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}
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*dma_handle = addr;
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return page_address(pg);
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}
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/*
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* Free memory that was allocated with tile_dma_alloc_coherent.
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*/
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static void tile_dma_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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struct dma_attrs *attrs)
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{
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homecache_free_pages((unsigned long)vaddr, get_order(size));
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}
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/*
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* The map routines "map" the specified address range for DMA
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* accesses. The memory belongs to the device after this call is
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* issued, until it is unmapped with dma_unmap_single.
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*
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* We don't need to do any mapping, we just flush the address range
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* out of the cache and return a DMA address.
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*
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* The unmap routines do whatever is necessary before the processor
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* accesses the memory again, and must be called before the driver
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* touches the memory. We can get away with a cache invalidate if we
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* can count on nothing having been touched.
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*/
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/* Set up a single page for DMA access. */
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static void __dma_prep_page(struct page *page, unsigned long offset,
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size_t size, enum dma_data_direction direction)
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{
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/*
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* Flush the page from cache if necessary.
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* On tilegx, data is delivered to hash-for-home L3; on tilepro,
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* data is delivered direct to memory.
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*
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* NOTE: If we were just doing DMA_TO_DEVICE we could optimize
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* this to be a "flush" not a "finv" and keep some of the
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* state in cache across the DMA operation, but it doesn't seem
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* worth creating the necessary flush_buffer_xxx() infrastructure.
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*/
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int home = page_home(page);
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switch (home) {
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case PAGE_HOME_HASH:
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#ifdef __tilegx__
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return;
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#endif
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break;
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case PAGE_HOME_UNCACHED:
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#ifdef __tilepro__
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return;
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#endif
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break;
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case PAGE_HOME_IMMUTABLE:
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/* Should be going to the device only. */
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BUG_ON(direction == DMA_FROM_DEVICE ||
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direction == DMA_BIDIRECTIONAL);
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return;
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case PAGE_HOME_INCOHERENT:
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/* Incoherent anyway, so no need to work hard here. */
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return;
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default:
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BUG_ON(home < 0 || home >= NR_CPUS);
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break;
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}
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homecache_finv_page(page);
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#ifdef DEBUG_ALIGNMENT
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/* Warn if the region isn't cacheline aligned. */
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if (offset & (L2_CACHE_BYTES - 1) || (size & (L2_CACHE_BYTES - 1)))
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pr_warn("Unaligned DMA to non-hfh memory: PA %#llx/%#lx\n",
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PFN_PHYS(page_to_pfn(page)) + offset, size);
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#endif
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}
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/* Make the page ready to be read by the core. */
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static void __dma_complete_page(struct page *page, unsigned long offset,
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size_t size, enum dma_data_direction direction)
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{
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#ifdef __tilegx__
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switch (page_home(page)) {
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case PAGE_HOME_HASH:
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/* I/O device delivered data the way the cpu wanted it. */
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break;
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case PAGE_HOME_INCOHERENT:
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/* Incoherent anyway, so no need to work hard here. */
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break;
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case PAGE_HOME_IMMUTABLE:
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/* Extra read-only copies are not a problem. */
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break;
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default:
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/* Flush the bogus hash-for-home I/O entries to memory. */
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homecache_finv_map_page(page, PAGE_HOME_HASH);
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break;
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}
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#endif
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}
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static void __dma_prep_pa_range(dma_addr_t dma_addr, size_t size,
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enum dma_data_direction direction)
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{
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struct page *page = pfn_to_page(PFN_DOWN(dma_addr));
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unsigned long offset = dma_addr & (PAGE_SIZE - 1);
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size_t bytes = min(size, (size_t)(PAGE_SIZE - offset));
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while (size != 0) {
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__dma_prep_page(page, offset, bytes, direction);
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size -= bytes;
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++page;
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offset = 0;
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bytes = min((size_t)PAGE_SIZE, size);
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}
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}
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static void __dma_complete_pa_range(dma_addr_t dma_addr, size_t size,
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enum dma_data_direction direction)
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{
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struct page *page = pfn_to_page(PFN_DOWN(dma_addr));
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unsigned long offset = dma_addr & (PAGE_SIZE - 1);
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size_t bytes = min(size, (size_t)(PAGE_SIZE - offset));
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while (size != 0) {
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__dma_complete_page(page, offset, bytes, direction);
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size -= bytes;
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++page;
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offset = 0;
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bytes = min((size_t)PAGE_SIZE, size);
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}
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}
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static int tile_dma_map_sg(struct device *dev, struct scatterlist *sglist,
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int nents, enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(nents == 0 || sglist->length == 0);
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for_each_sg(sglist, sg, nents, i) {
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sg->dma_address = sg_phys(sg);
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__dma_prep_pa_range(sg->dma_address, sg->length, direction);
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#ifdef CONFIG_NEED_SG_DMA_LENGTH
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sg->dma_length = sg->length;
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#endif
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}
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return nents;
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}
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static void tile_dma_unmap_sg(struct device *dev, struct scatterlist *sglist,
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int nents, enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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for_each_sg(sglist, sg, nents, i) {
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sg->dma_address = sg_phys(sg);
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__dma_complete_pa_range(sg->dma_address, sg->length,
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direction);
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}
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}
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static dma_addr_t tile_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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BUG_ON(!valid_dma_direction(direction));
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BUG_ON(offset + size > PAGE_SIZE);
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__dma_prep_page(page, offset, size, direction);
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return page_to_pa(page) + offset;
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}
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static void tile_dma_unmap_page(struct device *dev, dma_addr_t dma_address,
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size_t size, enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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BUG_ON(!valid_dma_direction(direction));
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__dma_complete_page(pfn_to_page(PFN_DOWN(dma_address)),
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dma_address & (PAGE_SIZE - 1), size, direction);
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}
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static void tile_dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle,
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size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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__dma_complete_pa_range(dma_handle, size, direction);
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}
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static void tile_dma_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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__dma_prep_pa_range(dma_handle, size, direction);
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}
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static void tile_dma_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sglist, int nelems,
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enum dma_data_direction direction)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(nelems == 0 || sglist->length == 0);
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for_each_sg(sglist, sg, nelems, i) {
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dma_sync_single_for_cpu(dev, sg->dma_address,
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sg_dma_len(sg), direction);
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}
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}
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static void tile_dma_sync_sg_for_device(struct device *dev,
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struct scatterlist *sglist, int nelems,
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enum dma_data_direction direction)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(nelems == 0 || sglist->length == 0);
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for_each_sg(sglist, sg, nelems, i) {
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dma_sync_single_for_device(dev, sg->dma_address,
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sg_dma_len(sg), direction);
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}
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}
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static inline int
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tile_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return 0;
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}
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static inline int
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tile_dma_supported(struct device *dev, u64 mask)
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{
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return 1;
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}
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static struct dma_map_ops tile_default_dma_map_ops = {
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.alloc = tile_dma_alloc_coherent,
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.free = tile_dma_free_coherent,
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.map_page = tile_dma_map_page,
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.unmap_page = tile_dma_unmap_page,
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.map_sg = tile_dma_map_sg,
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.unmap_sg = tile_dma_unmap_sg,
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.sync_single_for_cpu = tile_dma_sync_single_for_cpu,
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.sync_single_for_device = tile_dma_sync_single_for_device,
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.sync_sg_for_cpu = tile_dma_sync_sg_for_cpu,
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.sync_sg_for_device = tile_dma_sync_sg_for_device,
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.mapping_error = tile_dma_mapping_error,
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.dma_supported = tile_dma_supported
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};
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struct dma_map_ops *tile_dma_map_ops = &tile_default_dma_map_ops;
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EXPORT_SYMBOL(tile_dma_map_ops);
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/* Generic PCI DMA mapping functions */
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static void *tile_pci_dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp,
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struct dma_attrs *attrs)
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{
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int node = dev_to_node(dev);
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int order = get_order(size);
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struct page *pg;
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dma_addr_t addr;
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gfp |= __GFP_ZERO;
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pg = homecache_alloc_pages_node(node, gfp, order, PAGE_HOME_DMA);
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if (pg == NULL)
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return NULL;
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addr = page_to_phys(pg);
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*dma_handle = addr + get_dma_offset(dev);
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return page_address(pg);
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}
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/*
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* Free memory that was allocated with tile_pci_dma_alloc_coherent.
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*/
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static void tile_pci_dma_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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struct dma_attrs *attrs)
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{
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homecache_free_pages((unsigned long)vaddr, get_order(size));
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}
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static int tile_pci_dma_map_sg(struct device *dev, struct scatterlist *sglist,
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int nents, enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(nents == 0 || sglist->length == 0);
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for_each_sg(sglist, sg, nents, i) {
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sg->dma_address = sg_phys(sg);
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__dma_prep_pa_range(sg->dma_address, sg->length, direction);
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sg->dma_address = sg->dma_address + get_dma_offset(dev);
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#ifdef CONFIG_NEED_SG_DMA_LENGTH
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sg->dma_length = sg->length;
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#endif
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}
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return nents;
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}
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static void tile_pci_dma_unmap_sg(struct device *dev,
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struct scatterlist *sglist, int nents,
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enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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for_each_sg(sglist, sg, nents, i) {
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sg->dma_address = sg_phys(sg);
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__dma_complete_pa_range(sg->dma_address, sg->length,
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direction);
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}
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}
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static dma_addr_t tile_pci_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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BUG_ON(!valid_dma_direction(direction));
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BUG_ON(offset + size > PAGE_SIZE);
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__dma_prep_page(page, offset, size, direction);
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return page_to_pa(page) + offset + get_dma_offset(dev);
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}
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static void tile_pci_dma_unmap_page(struct device *dev, dma_addr_t dma_address,
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size_t size,
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enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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BUG_ON(!valid_dma_direction(direction));
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dma_address -= get_dma_offset(dev);
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__dma_complete_page(pfn_to_page(PFN_DOWN(dma_address)),
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dma_address & (PAGE_SIZE - 1), size, direction);
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}
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static void tile_pci_dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle,
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size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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dma_handle -= get_dma_offset(dev);
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__dma_complete_pa_range(dma_handle, size, direction);
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}
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static void tile_pci_dma_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle,
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size_t size,
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enum dma_data_direction
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direction)
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{
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dma_handle -= get_dma_offset(dev);
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__dma_prep_pa_range(dma_handle, size, direction);
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}
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static void tile_pci_dma_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sglist,
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int nelems,
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enum dma_data_direction direction)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(nelems == 0 || sglist->length == 0);
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for_each_sg(sglist, sg, nelems, i) {
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dma_sync_single_for_cpu(dev, sg->dma_address,
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sg_dma_len(sg), direction);
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}
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}
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static void tile_pci_dma_sync_sg_for_device(struct device *dev,
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struct scatterlist *sglist,
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int nelems,
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enum dma_data_direction direction)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(nelems == 0 || sglist->length == 0);
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for_each_sg(sglist, sg, nelems, i) {
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dma_sync_single_for_device(dev, sg->dma_address,
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sg_dma_len(sg), direction);
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}
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}
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static inline int
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tile_pci_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return 0;
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}
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static inline int
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tile_pci_dma_supported(struct device *dev, u64 mask)
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{
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return 1;
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}
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static struct dma_map_ops tile_pci_default_dma_map_ops = {
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.alloc = tile_pci_dma_alloc_coherent,
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.free = tile_pci_dma_free_coherent,
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.map_page = tile_pci_dma_map_page,
|
|
.unmap_page = tile_pci_dma_unmap_page,
|
|
.map_sg = tile_pci_dma_map_sg,
|
|
.unmap_sg = tile_pci_dma_unmap_sg,
|
|
.sync_single_for_cpu = tile_pci_dma_sync_single_for_cpu,
|
|
.sync_single_for_device = tile_pci_dma_sync_single_for_device,
|
|
.sync_sg_for_cpu = tile_pci_dma_sync_sg_for_cpu,
|
|
.sync_sg_for_device = tile_pci_dma_sync_sg_for_device,
|
|
.mapping_error = tile_pci_dma_mapping_error,
|
|
.dma_supported = tile_pci_dma_supported
|
|
};
|
|
|
|
struct dma_map_ops *gx_pci_dma_map_ops = &tile_pci_default_dma_map_ops;
|
|
EXPORT_SYMBOL(gx_pci_dma_map_ops);
|
|
|
|
/* PCI DMA mapping functions for legacy PCI devices */
|
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
static void *tile_swiotlb_alloc_coherent(struct device *dev, size_t size,
|
|
dma_addr_t *dma_handle, gfp_t gfp,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
gfp |= GFP_DMA;
|
|
return swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
|
|
}
|
|
|
|
static void tile_swiotlb_free_coherent(struct device *dev, size_t size,
|
|
void *vaddr, dma_addr_t dma_addr,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
swiotlb_free_coherent(dev, size, vaddr, dma_addr);
|
|
}
|
|
|
|
static struct dma_map_ops pci_swiotlb_dma_ops = {
|
|
.alloc = tile_swiotlb_alloc_coherent,
|
|
.free = tile_swiotlb_free_coherent,
|
|
.map_page = swiotlb_map_page,
|
|
.unmap_page = swiotlb_unmap_page,
|
|
.map_sg = swiotlb_map_sg_attrs,
|
|
.unmap_sg = swiotlb_unmap_sg_attrs,
|
|
.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
|
|
.sync_single_for_device = swiotlb_sync_single_for_device,
|
|
.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
|
|
.sync_sg_for_device = swiotlb_sync_sg_for_device,
|
|
.dma_supported = swiotlb_dma_supported,
|
|
.mapping_error = swiotlb_dma_mapping_error,
|
|
};
|
|
|
|
static struct dma_map_ops pci_hybrid_dma_ops = {
|
|
.alloc = tile_swiotlb_alloc_coherent,
|
|
.free = tile_swiotlb_free_coherent,
|
|
.map_page = tile_pci_dma_map_page,
|
|
.unmap_page = tile_pci_dma_unmap_page,
|
|
.map_sg = tile_pci_dma_map_sg,
|
|
.unmap_sg = tile_pci_dma_unmap_sg,
|
|
.sync_single_for_cpu = tile_pci_dma_sync_single_for_cpu,
|
|
.sync_single_for_device = tile_pci_dma_sync_single_for_device,
|
|
.sync_sg_for_cpu = tile_pci_dma_sync_sg_for_cpu,
|
|
.sync_sg_for_device = tile_pci_dma_sync_sg_for_device,
|
|
.mapping_error = tile_pci_dma_mapping_error,
|
|
.dma_supported = tile_pci_dma_supported
|
|
};
|
|
|
|
struct dma_map_ops *gx_legacy_pci_dma_map_ops = &pci_swiotlb_dma_ops;
|
|
struct dma_map_ops *gx_hybrid_pci_dma_map_ops = &pci_hybrid_dma_ops;
|
|
#else
|
|
struct dma_map_ops *gx_legacy_pci_dma_map_ops;
|
|
struct dma_map_ops *gx_hybrid_pci_dma_map_ops;
|
|
#endif
|
|
EXPORT_SYMBOL(gx_legacy_pci_dma_map_ops);
|
|
EXPORT_SYMBOL(gx_hybrid_pci_dma_map_ops);
|
|
|
|
#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
|
|
int dma_set_coherent_mask(struct device *dev, u64 mask)
|
|
{
|
|
struct dma_map_ops *dma_ops = get_dma_ops(dev);
|
|
|
|
/*
|
|
* For PCI devices with 64-bit DMA addressing capability, promote
|
|
* the dma_ops to full capability for both streams and consistent
|
|
* memory access. For 32-bit capable devices, limit the consistent
|
|
* memory DMA range to max_direct_dma_addr.
|
|
*/
|
|
if (dma_ops == gx_pci_dma_map_ops ||
|
|
dma_ops == gx_hybrid_pci_dma_map_ops ||
|
|
dma_ops == gx_legacy_pci_dma_map_ops) {
|
|
if (mask == DMA_BIT_MASK(64))
|
|
set_dma_ops(dev, gx_pci_dma_map_ops);
|
|
else if (mask > dev->archdata.max_direct_dma_addr)
|
|
mask = dev->archdata.max_direct_dma_addr;
|
|
}
|
|
|
|
if (!dma_supported(dev, mask))
|
|
return -EIO;
|
|
dev->coherent_dma_mask = mask;
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(dma_set_coherent_mask);
|
|
#endif
|
|
|
|
#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
|
|
/*
|
|
* The generic dma_get_required_mask() uses the highest physical address
|
|
* (max_pfn) to provide the hint to the PCI drivers regarding 32-bit or
|
|
* 64-bit DMA configuration. Since TILEGx has I/O TLB/MMU, allowing the
|
|
* DMAs to use the full 64-bit PCI address space and not limited by
|
|
* the physical memory space, we always let the PCI devices use
|
|
* 64-bit DMA if they have that capability, by returning the 64-bit
|
|
* DMA mask here. The device driver has the option to use 32-bit DMA if
|
|
* the device is not capable of 64-bit DMA.
|
|
*/
|
|
u64 dma_get_required_mask(struct device *dev)
|
|
{
|
|
return DMA_BIT_MASK(64);
|
|
}
|
|
EXPORT_SYMBOL_GPL(dma_get_required_mask);
|
|
#endif
|
|
|