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530 lines
16 KiB
530 lines
16 KiB
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* This file contains the functions and defines necessary to modify and use
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* the TILE page table tree.
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*/
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#ifndef _ASM_TILE_PGTABLE_H
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#define _ASM_TILE_PGTABLE_H
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#include <hv/hypervisor.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#include <linux/threads.h>
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/pfn.h>
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#include <asm/processor.h>
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#include <asm/fixmap.h>
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#include <asm/page.h>
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struct mm_struct;
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struct vm_area_struct;
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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extern pgd_t swapper_pg_dir[];
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extern pgprot_t swapper_pgprot;
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extern struct kmem_cache *pgd_cache;
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extern spinlock_t pgd_lock;
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extern struct list_head pgd_list;
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/*
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* The very last slots in the pgd_t are for addresses unusable by Linux
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* (pgd_addr_invalid() returns true). So we use them for the list structure.
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* The x86 code we are modelled on uses the page->private/index fields
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* (older 2.6 kernels) or the lru list (newer 2.6 kernels), but since
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* our pgds are so much smaller than a page, it seems a waste to
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* spend a whole page on each pgd.
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*/
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#define PGD_LIST_OFFSET \
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((PTRS_PER_PGD * sizeof(pgd_t)) - sizeof(struct list_head))
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#define pgd_to_list(pgd) \
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((struct list_head *)((char *)(pgd) + PGD_LIST_OFFSET))
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#define list_to_pgd(list) \
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((pgd_t *)((char *)(list) - PGD_LIST_OFFSET))
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extern void pgtable_cache_init(void);
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extern void paging_init(void);
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extern void set_page_homes(void);
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#define FIRST_USER_ADDRESS 0UL
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#define _PAGE_PRESENT HV_PTE_PRESENT
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#define _PAGE_HUGE_PAGE HV_PTE_PAGE
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#define _PAGE_SUPER_PAGE HV_PTE_SUPER
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#define _PAGE_READABLE HV_PTE_READABLE
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#define _PAGE_WRITABLE HV_PTE_WRITABLE
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#define _PAGE_EXECUTABLE HV_PTE_EXECUTABLE
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#define _PAGE_ACCESSED HV_PTE_ACCESSED
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#define _PAGE_DIRTY HV_PTE_DIRTY
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#define _PAGE_GLOBAL HV_PTE_GLOBAL
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#define _PAGE_USER HV_PTE_USER
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/*
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* All the "standard" bits. Cache-control bits are managed elsewhere.
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* This is used to test for valid level-2 page table pointers by checking
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* all the bits, and to mask away the cache control bits for mprotect.
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*/
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#define _PAGE_ALL (\
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_PAGE_PRESENT | \
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_PAGE_HUGE_PAGE | \
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_PAGE_SUPER_PAGE | \
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_PAGE_READABLE | \
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_PAGE_WRITABLE | \
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_PAGE_EXECUTABLE | \
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_PAGE_ACCESSED | \
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_PAGE_DIRTY | \
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_PAGE_GLOBAL | \
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_PAGE_USER \
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)
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#define PAGE_NONE \
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__pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
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#define PAGE_SHARED \
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__pgprot(_PAGE_PRESENT | _PAGE_READABLE | _PAGE_WRITABLE | \
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_PAGE_USER | _PAGE_ACCESSED)
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#define PAGE_SHARED_EXEC \
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__pgprot(_PAGE_PRESENT | _PAGE_READABLE | _PAGE_WRITABLE | \
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_PAGE_EXECUTABLE | _PAGE_USER | _PAGE_ACCESSED)
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#define PAGE_COPY_NOEXEC \
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__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_READABLE)
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#define PAGE_COPY_EXEC \
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__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | \
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_PAGE_READABLE | _PAGE_EXECUTABLE)
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#define PAGE_COPY \
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PAGE_COPY_NOEXEC
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#define PAGE_READONLY \
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__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_READABLE)
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#define PAGE_READONLY_EXEC \
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__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | \
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_PAGE_READABLE | _PAGE_EXECUTABLE)
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#define _PAGE_KERNEL_RO \
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(_PAGE_PRESENT | _PAGE_GLOBAL | _PAGE_READABLE | _PAGE_ACCESSED)
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#define _PAGE_KERNEL \
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(_PAGE_KERNEL_RO | _PAGE_WRITABLE | _PAGE_DIRTY)
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#define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXECUTABLE)
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#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
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#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
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#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
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#define page_to_kpgprot(p) PAGE_KERNEL
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/*
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* We could tighten these up, but for now writable or executable
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* implies readable.
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*/
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY
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#define __P010 PAGE_COPY /* this is write-only, which we won't support */
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#define __P011 PAGE_COPY
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#define __P100 PAGE_READONLY_EXEC
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#define __P101 PAGE_READONLY_EXEC
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#define __P110 PAGE_COPY_EXEC
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#define __P111 PAGE_COPY_EXEC
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY
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#define __S010 PAGE_SHARED
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_READONLY_EXEC
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#define __S101 PAGE_READONLY_EXEC
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#define __S110 PAGE_SHARED_EXEC
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#define __S111 PAGE_SHARED_EXEC
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/*
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* All the normal _PAGE_ALL bits are ignored for PMDs, except PAGE_PRESENT
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* and PAGE_HUGE_PAGE, which must be one and zero, respectively.
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* We set the ignored bits to zero.
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*/
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#define _PAGE_TABLE _PAGE_PRESENT
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/* Inherit the caching flags from the old protection bits. */
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#define pgprot_modify(oldprot, newprot) \
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(pgprot_t) { ((oldprot).val & ~_PAGE_ALL) | (newprot).val }
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/* Just setting the PFN to zero suffices. */
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#define pte_pgprot(x) hv_pte_set_pa((x), 0)
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/*
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* For PTEs and PDEs, we must clear the Present bit first when
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* clearing a page table entry, so clear the bottom half first and
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* enforce ordering with a barrier.
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*/
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static inline void __pte_clear(pte_t *ptep)
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{
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#ifdef __tilegx__
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ptep->val = 0;
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#else
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u32 *tmp = (u32 *)ptep;
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tmp[0] = 0;
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barrier();
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tmp[1] = 0;
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#endif
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}
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#define pte_clear(mm, addr, ptep) __pte_clear(ptep)
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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#define pte_present hv_pte_get_present
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#define pte_mknotpresent hv_pte_clear_present
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#define pte_user hv_pte_get_user
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#define pte_read hv_pte_get_readable
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#define pte_dirty hv_pte_get_dirty
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#define pte_young hv_pte_get_accessed
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#define pte_write hv_pte_get_writable
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#define pte_exec hv_pte_get_executable
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#define pte_huge hv_pte_get_page
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#define pte_super hv_pte_get_super
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#define pte_rdprotect hv_pte_clear_readable
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#define pte_exprotect hv_pte_clear_executable
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#define pte_mkclean hv_pte_clear_dirty
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#define pte_mkold hv_pte_clear_accessed
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#define pte_wrprotect hv_pte_clear_writable
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#define pte_mksmall hv_pte_clear_page
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#define pte_mkread hv_pte_set_readable
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#define pte_mkexec hv_pte_set_executable
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#define pte_mkdirty hv_pte_set_dirty
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#define pte_mkyoung hv_pte_set_accessed
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#define pte_mkwrite hv_pte_set_writable
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#define pte_mkhuge hv_pte_set_page
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#define pte_mksuper hv_pte_set_super
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#define pte_special(pte) 0
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#define pte_mkspecial(pte) (pte)
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/*
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* Use some spare bits in the PTE for user-caching tags.
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*/
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#define pte_set_forcecache hv_pte_set_client0
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#define pte_get_forcecache hv_pte_get_client0
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#define pte_clear_forcecache hv_pte_clear_client0
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#define pte_set_anyhome hv_pte_set_client1
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#define pte_get_anyhome hv_pte_get_client1
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#define pte_clear_anyhome hv_pte_clear_client1
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/*
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* A migrating PTE has PAGE_PRESENT clear but all the other bits preserved.
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*/
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#define pte_migrating hv_pte_get_migrating
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#define pte_mkmigrate(x) hv_pte_set_migrating(hv_pte_clear_present(x))
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#define pte_donemigrate(x) hv_pte_set_present(hv_pte_clear_migrating(x))
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte 0x%016llx\n", __FILE__, __LINE__, pte_val(e))
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd 0x%016llx\n", __FILE__, __LINE__, pgd_val(e))
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/* Return PA and protection info for a given kernel VA. */
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int va_to_cpa_and_pte(void *va, phys_addr_t *cpa, pte_t *pte);
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/*
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* __set_pte() ensures we write the 64-bit PTE with 32-bit words in
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* the right order on 32-bit platforms and also allows us to write
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* hooks to check valid PTEs, etc., if we want.
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*/
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void __set_pte(pte_t *ptep, pte_t pte);
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/*
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* set_pte() sets the given PTE and also sanity-checks the
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* requested PTE against the page homecaching. Unspecified parts
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* of the PTE are filled in when it is written to memory, i.e. all
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* caching attributes if "!forcecache", or the home cpu if "anyhome".
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*/
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extern void set_pte(pte_t *ptep, pte_t pte);
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#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
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#define set_pte_atomic(pteptr, pteval) set_pte(pteptr, pteval)
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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static inline int pte_none(pte_t pte)
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{
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return !pte.val;
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}
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static inline unsigned long pte_pfn(pte_t pte)
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{
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return PFN_DOWN(hv_pte_get_pa(pte));
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}
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/* Set or get the remote cache cpu in a pgprot with remote caching. */
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extern pgprot_t set_remote_cache_cpu(pgprot_t prot, int cpu);
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extern int get_remote_cache_cpu(pgprot_t prot);
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
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{
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return hv_pte_set_pa(prot, PFN_PHYS(pfn));
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}
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/* Support for priority mappings. */
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extern void start_mm_caching(struct mm_struct *mm);
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extern void check_mm_caching(struct mm_struct *prev, struct mm_struct *next);
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/*
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* Encode and de-code a swap entry (see <linux/swapops.h>).
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* We put the swap file type+offset in the 32 high bits;
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* I believe we can just leave the low bits clear.
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*/
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#define __swp_type(swp) ((swp).val & 0x1f)
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#define __swp_offset(swp) ((swp).val >> 5)
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#define __swp_entry(type, off) ((swp_entry_t) { (type) | ((off) << 5) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).val >> 32 })
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#define __swp_entry_to_pte(swp) ((pte_t) { (((long long) ((swp).val)) << 32) })
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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/*
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* If we are doing an mprotect(), just accept the new vma->vm_page_prot
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* value and combine it with the PFN from the old PTE to get a new PTE.
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*/
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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return pfn_pte(pte_pfn(pte), newprot);
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}
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/*
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* The pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
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*
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* This macro returns the index of the entry in the pgd page which would
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* control the given virtual address.
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*/
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#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
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/*
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* pgd_offset() returns a (pgd_t *)
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* pgd_index() is used get the offset into the pgd page's array of pgd_t's.
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*/
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#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
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/*
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* A shortcut which implies the use of the kernel's pgd, instead
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* of a process's.
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*/
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
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#define pte_unmap(pte) do { } while (0)
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/* Clear a non-executable kernel PTE and flush it from the TLB. */
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#define kpte_clear_flush(ptep, vaddr) \
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do { \
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pte_clear(&init_mm, (vaddr), (ptep)); \
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local_flush_tlb_page(FLUSH_NONEXEC, (vaddr), PAGE_SIZE); \
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} while (0)
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/*
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* The kernel page tables contain what we need, and we flush when we
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* change specific page table entries.
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*/
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#define update_mmu_cache(vma, address, pte) do { } while (0)
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#ifdef CONFIG_FLATMEM
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#define kern_addr_valid(addr) (1)
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#endif /* CONFIG_FLATMEM */
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extern void vmalloc_sync_all(void);
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#endif /* !__ASSEMBLY__ */
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#ifdef __tilegx__
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#include <asm/pgtable_64.h>
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#else
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#include <asm/pgtable_32.h>
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#endif
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#ifndef __ASSEMBLY__
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static inline int pmd_none(pmd_t pmd)
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{
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/*
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* Only check low word on 32-bit platforms, since it might be
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* out of sync with upper half.
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*/
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return (unsigned long)pmd_val(pmd) == 0;
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}
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static inline int pmd_present(pmd_t pmd)
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{
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return pmd_val(pmd) & _PAGE_PRESENT;
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}
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static inline int pmd_bad(pmd_t pmd)
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{
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return ((pmd_val(pmd) & _PAGE_ALL) != _PAGE_TABLE);
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}
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static inline unsigned long pages_to_mb(unsigned long npg)
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{
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return npg >> (20 - PAGE_SHIFT);
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}
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/*
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* The pmd can be thought of an array like this: pmd_t[PTRS_PER_PMD]
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*
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* This function returns the index of the entry in the pmd which would
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* control the given virtual address.
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*/
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static inline unsigned long pmd_index(unsigned long address)
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{
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return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
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}
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#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
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static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
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unsigned long address,
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pmd_t *pmdp)
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{
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return ptep_test_and_clear_young(vma, address, pmdp_ptep(pmdp));
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}
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#define __HAVE_ARCH_PMDP_SET_WRPROTECT
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static inline void pmdp_set_wrprotect(struct mm_struct *mm,
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unsigned long address, pmd_t *pmdp)
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{
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ptep_set_wrprotect(mm, address, pmdp_ptep(pmdp));
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}
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#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
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static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
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unsigned long address,
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pmd_t *pmdp)
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{
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return pte_pmd(ptep_get_and_clear(mm, address, pmdp_ptep(pmdp)));
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}
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static inline void __set_pmd(pmd_t *pmdp, pmd_t pmdval)
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{
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set_pte(pmdp_ptep(pmdp), pmd_pte(pmdval));
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}
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#define set_pmd_at(mm, addr, pmdp, pmdval) __set_pmd(pmdp, pmdval)
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/* Create a pmd from a PTFN. */
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static inline pmd_t ptfn_pmd(unsigned long ptfn, pgprot_t prot)
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{
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return pte_pmd(hv_pte_set_ptfn(prot, ptfn));
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}
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/* Return the page-table frame number (ptfn) that a pmd_t points at. */
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#define pmd_ptfn(pmd) hv_pte_get_ptfn(pmd_pte(pmd))
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/*
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* A given kernel pmd_t maps to a specific virtual address (either a
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* kernel huge page or a kernel pte_t table). Since kernel pte_t
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* tables can be aligned at sub-page granularity, this function can
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* return non-page-aligned pointers, despite its name.
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*/
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static inline unsigned long pmd_page_vaddr(pmd_t pmd)
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{
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phys_addr_t pa =
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(phys_addr_t)pmd_ptfn(pmd) << HV_LOG2_PAGE_TABLE_ALIGN;
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return (unsigned long)__va(pa);
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}
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/*
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* A pmd_t points to the base of a huge page or to a pte_t array.
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* If a pte_t array, since we can have multiple per page, we don't
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* have a one-to-one mapping of pmd_t's to pages. However, this is
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* OK for pte_lockptr(), since we just end up with potentially one
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* lock being used for several pte_t arrays.
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*/
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#define pmd_page(pmd) pfn_to_page(PFN_DOWN(HV_PTFN_TO_CPA(pmd_ptfn(pmd))))
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static inline void pmd_clear(pmd_t *pmdp)
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{
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__pte_clear(pmdp_ptep(pmdp));
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}
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#define pmd_mknotpresent(pmd) pte_pmd(pte_mknotpresent(pmd_pte(pmd)))
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#define pmd_young(pmd) pte_young(pmd_pte(pmd))
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#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
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#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
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#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
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#define pmd_write(pmd) pte_write(pmd_pte(pmd))
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#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
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#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
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#define pmd_huge_page(pmd) pte_huge(pmd_pte(pmd))
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#define pmd_mkhuge(pmd) pte_pmd(pte_mkhuge(pmd_pte(pmd)))
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#define __HAVE_ARCH_PMD_WRITE
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#define pfn_pmd(pfn, pgprot) pte_pmd(pfn_pte((pfn), (pgprot)))
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#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
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#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
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static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
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{
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return pfn_pmd(pmd_pfn(pmd), newprot);
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}
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|
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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#define has_transparent_hugepage() 1
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#define pmd_trans_huge pmd_huge_page
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static inline pmd_t pmd_mksplitting(pmd_t pmd)
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{
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return pte_pmd(hv_pte_set_client2(pmd_pte(pmd)));
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}
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|
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static inline int pmd_trans_splitting(pmd_t pmd)
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|
{
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return hv_pte_get_client2(pmd_pte(pmd));
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}
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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|
|
|
/*
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|
* The pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
|
|
*
|
|
* This macro returns the index of the entry in the pte page which would
|
|
* control the given virtual address.
|
|
*/
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|
static inline unsigned long pte_index(unsigned long address)
|
|
{
|
|
return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
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|
}
|
|
|
|
static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address)
|
|
{
|
|
return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address);
|
|
}
|
|
|
|
#include <asm-generic/pgtable.h>
|
|
|
|
/* Support /proc/NN/pgtable API. */
|
|
struct seq_file;
|
|
int arch_proc_pgtable_show(struct seq_file *m, struct mm_struct *mm,
|
|
unsigned long vaddr, unsigned long pagesize,
|
|
pte_t *ptep, void **datap);
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
#endif /* _ASM_TILE_PGTABLE_H */
|
|
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