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117 lines
4.6 KiB
117 lines
4.6 KiB
/*
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* A collection of structures, addresses, and values associated with
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* the Motorola MBX boards. This was originally created for the
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* MBX860, and probably needs revisions for other boards (like the 821).
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* When this file gets out of control, we can split it up into more
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* meaningful pieces.
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*
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* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
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*/
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#ifdef __KERNEL__
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#ifndef __MACH_MBX_DEFS
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#define __MACH_MBX_DEFS
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#ifndef __ASSEMBLY__
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/* A Board Information structure that is given to a program when
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* EPPC-Bug starts it up.
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*/
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typedef struct bd_info {
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unsigned int bi_tag; /* Should be 0x42444944 "BDID" */
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unsigned int bi_size; /* Size of this structure */
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unsigned int bi_revision; /* revision of this structure */
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unsigned int bi_bdate; /* EPPCbug date, i.e. 0x11061997 */
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unsigned int bi_memstart; /* Memory start address */
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unsigned int bi_memsize; /* Memory (end) size in bytes */
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unsigned int bi_intfreq; /* Internal Freq, in Hz */
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unsigned int bi_busfreq; /* Bus Freq, in Hz */
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unsigned int bi_clun; /* Boot device controller */
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unsigned int bi_dlun; /* Boot device logical dev */
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/* These fields are not part of the board information structure
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* provided by the boot rom. They are filled in by embed_config.c
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* so we have the information consistent with other platforms.
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*/
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unsigned char bi_enetaddr[6];
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unsigned int bi_baudrate;
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} bd_t;
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/* Memory map for the MBX as configured by EPPC-Bug. We could reprogram
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* The SIU and PCI bridge, and try to use larger MMU pages, but the
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* performance gain is not measureable and it certainly complicates the
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* generic MMU model.
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*
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* In a effort to minimize memory usage for embedded applications, any
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* PCI driver or ISA driver must request or map the region required by
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* the device. For convenience (and since we can map up to 4 Mbytes with
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* a single page table page), the MMU initialization will map the
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* NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI
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* Bridge CSRs 1:1 into the kernel address space.
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*/
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#define PCI_ISA_IO_ADDR ((unsigned)0x80000000)
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#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024))
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#define PCI_IDE_ADDR ((unsigned)0x81000000)
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#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000)
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#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024))
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#define PCMCIA_MEM_ADDR ((uint)0xe0000000)
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#define PCMCIA_MEM_SIZE ((uint)(64 * 1024 * 1024))
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#define PCMCIA_DMA_ADDR ((uint)0xe4000000)
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#define PCMCIA_DMA_SIZE ((uint)(64 * 1024 * 1024))
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#define PCMCIA_ATTRB_ADDR ((uint)0xe8000000)
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#define PCMCIA_ATTRB_SIZE ((uint)(64 * 1024 * 1024))
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#define PCMCIA_IO_ADDR ((uint)0xec000000)
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#define PCMCIA_IO_SIZE ((uint)(64 * 1024 * 1024))
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#define NVRAM_ADDR ((uint)0xfa000000)
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#define NVRAM_SIZE ((uint)(1 * 1024 * 1024))
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#define MBX_CSR_ADDR ((uint)0xfa100000)
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#define MBX_CSR_SIZE ((uint)(1 * 1024 * 1024))
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#define IMAP_ADDR ((uint)0xfa200000)
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#define IMAP_SIZE ((uint)(64 * 1024))
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#define PCI_CSR_ADDR ((uint)0xfa210000)
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#define PCI_CSR_SIZE ((uint)(64 * 1024))
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/* Map additional physical space into well known virtual addresses. Due
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* to virtual address mapping, these physical addresses are not accessible
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* in a 1:1 virtual to physical mapping.
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*/
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#define ISA_IO_VIRT_ADDR ((uint)0xfa220000)
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#define ISA_IO_VIRT_SIZE ((uint)64 * 1024)
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/* Interrupt assignments.
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* These are defined (and fixed) by the MBX hardware implementation.
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*/
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#define POWER_FAIL_INT SIU_IRQ0 /* Power fail */
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#define TEMP_HILO_INT SIU_IRQ1 /* Temperature sensor */
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#define QSPAN_INT SIU_IRQ2 /* PCI Bridge (DMA CTLR?) */
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#define ISA_BRIDGE_INT SIU_IRQ3 /* All those PC things */
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#define COMM_L_INT SIU_IRQ6 /* MBX Comm expansion connector pin */
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#define STOP_ABRT_INT SIU_IRQ7 /* Stop/Abort header pin */
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/* CPM Ethernet through SCCx.
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*
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* Bits in parallel I/O port registers that have to be set/cleared
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* to configure the pins for SCC1 use. The TCLK and RCLK seem unique
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* to the MBX860 board. Any two of the four available clocks could be
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* used, and the MPC860 cookbook manual has an example using different
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* clock pins.
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*/
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#define PA_ENET_RXD ((ushort)0x0001)
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#define PA_ENET_TXD ((ushort)0x0002)
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#define PA_ENET_TCLK ((ushort)0x0200)
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#define PA_ENET_RCLK ((ushort)0x0800)
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#define PC_ENET_TENA ((ushort)0x0001)
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#define PC_ENET_CLSN ((ushort)0x0010)
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#define PC_ENET_RENA ((ushort)0x0020)
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/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
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* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
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*/
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#define SICR_ENET_MASK ((uint)0x000000ff)
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#define SICR_ENET_CLKRT ((uint)0x0000003d)
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/* The MBX uses the 8259.
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*/
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#define NR_8259_INTS 16
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#endif /* !__ASSEMBLY__ */
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#endif /* __MACH_MBX_DEFS */
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#endif /* __KERNEL__ */
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