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456 lines
15 KiB
456 lines
15 KiB
/******************************************************************************
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*
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* Name: skdrv2nd.h
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* Project: GEnesis, PCI Gigabit Ethernet Adapter
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* Version: $Revision: 1.10 $
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* Date: $Date: 2003/12/11 16:04:45 $
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* Purpose: Second header file for driver and all other modules
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*
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******************************************************************************/
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/******************************************************************************
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*
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* (C)Copyright 1998-2002 SysKonnect GmbH.
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* (C)Copyright 2002-2003 Marvell.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* The information in this file is provided "AS IS" without warranty.
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*
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******************************************************************************/
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/******************************************************************************
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*
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* Description:
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*
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* This is the second include file of the driver, which includes all other
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* neccessary files and defines all structures and constants used by the
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* driver and the common modules.
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*
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* Include File Hierarchy:
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*
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* see skge.c
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*
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******************************************************************************/
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#ifndef __INC_SKDRV2ND_H
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#define __INC_SKDRV2ND_H
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#include "h/skqueue.h"
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#include "h/skgehwt.h"
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#include "h/sktimer.h"
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#include "h/ski2c.h"
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#include "h/skgepnmi.h"
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#include "h/skvpd.h"
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#include "h/skgehw.h"
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#include "h/skgeinit.h"
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#include "h/skaddr.h"
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#include "h/skgesirq.h"
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#include "h/skcsum.h"
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#include "h/skrlmt.h"
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#include "h/skgedrv.h"
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extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
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extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
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extern SK_U64 SkOsGetTime(SK_AC*);
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extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
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extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
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extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
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extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32);
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extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
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extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
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extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
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#ifdef SK_DIAG_SUPPORT
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extern int SkDrvEnterDiagMode(SK_AC *pAc);
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extern int SkDrvLeaveDiagMode(SK_AC *pAc);
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#endif
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struct s_DrvRlmtMbuf {
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SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
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SK_U8 *pData; /* Data buffer (virtually contig.). */
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unsigned Size; /* Data buffer size. */
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unsigned Length; /* Length of packet (<= Size). */
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SK_U32 PortIdx; /* Receiving/transmitting port. */
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#ifdef SK_RLMT_MBUF_PRIVATE
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SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
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#endif /* SK_RLMT_MBUF_PRIVATE */
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struct sk_buff *pOs; /* Pointer to message block */
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};
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/*
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* Time macros
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*/
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#if SK_TICKS_PER_SEC == 100
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#define SK_PNMI_HUNDREDS_SEC(t) (t)
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#else
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#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t) * 100) / \
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(SK_TICKS_PER_SEC))
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#endif
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/*
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* New SkOsGetTime
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*/
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#define SkOsGetTimeCurrent(pAC, pUsec) {\
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struct timeval t;\
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do_gettimeofday(&t);\
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*pUsec = ((((t.tv_sec) * 1000000L)+t.tv_usec)/10000);\
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}
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/*
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* ioctl definitions
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*/
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#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
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#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
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#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
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#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
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#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
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#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4)
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typedef struct s_IOCTL SK_GE_IOCTL;
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struct s_IOCTL {
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char __user * pData;
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unsigned int Len;
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};
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/*
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* define sizes of descriptor rings in bytes
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*/
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#define TX_RING_SIZE (8*1024)
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#define RX_RING_SIZE (24*1024)
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/*
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* Buffer size for ethernet packets
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*/
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#define ETH_BUF_SIZE 1540
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#define ETH_MAX_MTU 1514
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#define ETH_MIN_MTU 60
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#define ETH_MULTICAST_BIT 0x01
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#define SK_JUMBO_MTU 9000
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/*
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* transmit priority selects the queue: LOW=asynchron, HIGH=synchron
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*/
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#define TX_PRIO_LOW 0
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#define TX_PRIO_HIGH 1
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/*
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* alignment of rx/tx descriptors
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*/
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#define DESCR_ALIGN 64
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/*
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* definitions for pnmi. TODO
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*/
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#define SK_DRIVER_RESET(pAC, IoC) 0
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#define SK_DRIVER_SENDEVENT(pAC, IoC) 0
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#define SK_DRIVER_SELFTEST(pAC, IoC) 0
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/* For get mtu you must add an own function */
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#define SK_DRIVER_GET_MTU(pAc,IoC,i) 0
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#define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0
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#define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0
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/*
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** Interim definition of SK_DRV_TIMER placed in this file until
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** common modules have boon finallized
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*/
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#define SK_DRV_TIMER 11
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#define SK_DRV_MODERATION_TIMER 1
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#define SK_DRV_MODERATION_TIMER_LENGTH 1000000 /* 1 second */
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#define SK_DRV_RX_CLEANUP_TIMER 2
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#define SK_DRV_RX_CLEANUP_TIMER_LENGTH 1000000 /* 100 millisecs */
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/*
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** Definitions regarding transmitting frames
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** any calculating any checksum.
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*/
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#define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6
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#define C_LEN_ETHERMAC_HEADER_SRC_ADDR 6
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#define C_LEN_ETHERMAC_HEADER_LENTYPE 2
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#define C_LEN_ETHERMAC_HEADER ( (C_LEN_ETHERMAC_HEADER_DEST_ADDR) + \
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(C_LEN_ETHERMAC_HEADER_SRC_ADDR) + \
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(C_LEN_ETHERMAC_HEADER_LENTYPE) )
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#define C_LEN_ETHERMTU_MINSIZE 46
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#define C_LEN_ETHERMTU_MAXSIZE_STD 1500
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#define C_LEN_ETHERMTU_MAXSIZE_JUMBO 9000
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#define C_LEN_ETHERNET_MINSIZE ( (C_LEN_ETHERMAC_HEADER) + \
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(C_LEN_ETHERMTU_MINSIZE) )
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#define C_OFFSET_IPHEADER C_LEN_ETHERMAC_HEADER
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#define C_OFFSET_IPHEADER_IPPROTO 9
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#define C_OFFSET_TCPHEADER_TCPCS 16
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#define C_OFFSET_UDPHEADER_UDPCS 6
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#define C_OFFSET_IPPROTO ( (C_LEN_ETHERMAC_HEADER) + \
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(C_OFFSET_IPHEADER_IPPROTO) )
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#define C_PROTO_ID_UDP 17 /* refer to RFC 790 or Stevens' */
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#define C_PROTO_ID_TCP 6 /* TCP/IP illustrated for details */
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/* TX and RX descriptors *****************************************************/
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typedef struct s_RxD RXD; /* the receive descriptor */
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struct s_RxD {
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volatile SK_U32 RBControl; /* Receive Buffer Control */
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SK_U32 VNextRxd; /* Next receive descriptor,low dword */
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SK_U32 VDataLow; /* Receive buffer Addr, low dword */
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SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
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SK_U32 FrameStat; /* Receive Frame Status word */
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SK_U32 TimeStamp; /* Time stamp from XMAC */
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SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
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SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
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RXD *pNextRxd; /* Pointer to next Rxd */
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struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
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};
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typedef struct s_TxD TXD; /* the transmit descriptor */
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struct s_TxD {
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volatile SK_U32 TBControl; /* Transmit Buffer Control */
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SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
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SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
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SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
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SK_U32 FrameStat; /* Transmit Frame Status Word */
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SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
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SK_U16 TcpSumSt; /* TCP Sum Start */
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SK_U16 TcpSumWr; /* TCP Sum Write */
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SK_U32 TcpReserved; /* not used */
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TXD *pNextTxd; /* Pointer to next Txd */
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struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
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};
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/* Used interrupt bits in the interrupts source register *********************/
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#define DRIVER_IRQS ((IS_IRQ_SW) | \
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(IS_R1_F) |(IS_R2_F) | \
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(IS_XS1_F) |(IS_XA1_F) | \
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(IS_XS2_F) |(IS_XA2_F))
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#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
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(IS_EXT_REG) |(IS_TIMINT) | \
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(IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
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(IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
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(IS_MAC1) |(IS_LNK_SYNC_M1)| \
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(IS_MAC2) |(IS_LNK_SYNC_M2)| \
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(IS_R1_C) |(IS_R2_C) | \
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(IS_XS1_C) |(IS_XA1_C) | \
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(IS_XS2_C) |(IS_XA2_C))
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#define IRQ_MASK ((IS_IRQ_SW) | \
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(IS_R1_B) |(IS_R1_F) |(IS_R2_B) |(IS_R2_F) | \
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(IS_XS1_B) |(IS_XS1_F) |(IS_XA1_B)|(IS_XA1_F)| \
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(IS_XS2_B) |(IS_XS2_F) |(IS_XA2_B)|(IS_XA2_F)| \
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(IS_HW_ERR) |(IS_I2C_READY)| \
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(IS_EXT_REG) |(IS_TIMINT) | \
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(IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
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(IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
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(IS_MAC1) |(IS_MAC2) | \
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(IS_R1_C) |(IS_R2_C) | \
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(IS_XS1_C) |(IS_XA1_C) | \
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(IS_XS2_C) |(IS_XA2_C))
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#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */
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typedef struct s_DevNet DEV_NET;
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struct s_DevNet {
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int PortNr;
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int NetNr;
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int Mtu;
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int Up;
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SK_AC *pAC;
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};
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typedef struct s_TxPort TX_PORT;
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struct s_TxPort {
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/* the transmit descriptor rings */
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caddr_t pTxDescrRing; /* descriptor area memory */
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SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
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TXD *pTxdRingHead; /* Head of Tx rings */
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TXD *pTxdRingTail; /* Tail of Tx rings */
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TXD *pTxdRingPrev; /* descriptor sent previously */
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int TxdRingFree; /* # of free entrys */
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spinlock_t TxDesRingLock; /* serialize descriptor accesses */
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SK_IOC HwAddr; /* bmu registers address */
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int PortIndex; /* index number of port (0 or 1) */
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};
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typedef struct s_RxPort RX_PORT;
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struct s_RxPort {
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/* the receive descriptor rings */
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caddr_t pRxDescrRing; /* descriptor area memory */
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SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
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RXD *pRxdRingHead; /* Head of Rx rings */
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RXD *pRxdRingTail; /* Tail of Rx rings */
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RXD *pRxdRingPrev; /* descriptor given to BMU previously */
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int RxdRingFree; /* # of free entrys */
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spinlock_t RxDesRingLock; /* serialize descriptor accesses */
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int RxFillLimit; /* limit for buffers in ring */
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SK_IOC HwAddr; /* bmu registers address */
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int PortIndex; /* index number of port (0 or 1) */
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};
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/* Definitions needed for interrupt moderation *******************************/
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#define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F))
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#define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F))
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#define IRQ_MASK_TX_ONLY ((IRQ_EOF_AS_TX)| (IRQ_EOF_SY_TX))
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#define IRQ_MASK_RX_ONLY ((IS_R1_F) | (IS_R2_F))
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#define IRQ_MASK_SP_ONLY (SPECIAL_IRQS)
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#define IRQ_MASK_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))
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#define IRQ_MASK_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY))
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#define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
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#define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
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#define C_INT_MOD_NONE 1
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#define C_INT_MOD_STATIC 2
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#define C_INT_MOD_DYNAMIC 4
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#define C_CLK_FREQ_GENESIS 53215000 /* shorter: 53.125 MHz */
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#define C_CLK_FREQ_YUKON 78215000 /* shorter: 78.125 MHz */
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#define C_INTS_PER_SEC_DEFAULT 2000
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#define C_INT_MOD_ENABLE_PERCENTAGE 50 /* if higher 50% enable */
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#define C_INT_MOD_DISABLE_PERCENTAGE 50 /* if lower 50% disable */
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#define C_INT_MOD_IPS_LOWER_RANGE 30
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#define C_INT_MOD_IPS_UPPER_RANGE 40000
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typedef struct s_DynIrqModInfo DIM_INFO;
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struct s_DynIrqModInfo {
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unsigned long PrevTimeVal;
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unsigned int PrevSysLoad;
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unsigned int PrevUsedTime;
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unsigned int PrevTotalTime;
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int PrevUsedDescrRatio;
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int NbrProcessedDescr;
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SK_U64 PrevPort0RxIntrCts;
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SK_U64 PrevPort1RxIntrCts;
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SK_U64 PrevPort0TxIntrCts;
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SK_U64 PrevPort1TxIntrCts;
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SK_BOOL ModJustEnabled; /* Moderation just enabled yes/no */
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int MaxModIntsPerSec; /* Moderation Threshold */
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int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */
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int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */
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long MaskIrqModeration; /* ModIrqType (eg. 'TxRx') */
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SK_BOOL DisplayStats; /* Stats yes/no */
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SK_BOOL AutoSizing; /* Resize DIM-timer on/off */
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int IntModTypeSelect; /* EnableIntMod (eg. 'dynamic') */
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SK_TIMER ModTimer; /* just some timer */
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};
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typedef struct s_PerStrm PER_STRM;
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#define SK_ALLOC_IRQ 0x00000001
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#ifdef SK_DIAG_SUPPORT
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#define DIAG_ACTIVE 1
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#define DIAG_NOTACTIVE 0
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#endif
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/****************************************************************************
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* Per board structure / Adapter Context structure:
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* Allocated within attach(9e) and freed within detach(9e).
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* Contains all 'per device' necessary handles, flags, locks etc.:
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*/
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struct s_AC {
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SK_GEINIT GIni; /* GE init struct */
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SK_PNMI Pnmi; /* PNMI data struct */
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SK_VPD vpd; /* vpd data struct */
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SK_QUEUE Event; /* Event queue */
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SK_HWT Hwt; /* Hardware Timer control struct */
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SK_TIMCTRL Tim; /* Software Timer control struct */
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SK_I2C I2c; /* I2C relevant data structure */
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SK_ADDR Addr; /* for Address module */
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SK_CSUM Csum; /* for checksum module */
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SK_RLMT Rlmt; /* for rlmt module */
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spinlock_t SlowPathLock; /* Normal IRQ lock */
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struct timer_list BlinkTimer; /* for LED blinking */
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int LedsOn;
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SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
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int RlmtMode; /* link check mode to set */
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int RlmtNets; /* Number of nets */
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SK_IOC IoBase; /* register set of adapter */
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int BoardLevel; /* level of active hw init (0-2) */
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char DeviceStr[80]; /* adapter string from vpd */
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SK_U32 AllocFlag; /* flag allocation of resources */
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struct pci_dev *PciDev; /* for access to pci config space */
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SK_U32 PciDevId; /* pci device id */
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struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */
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char Name[30]; /* driver name */
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int RxBufSize; /* length of receive buffers */
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struct net_device_stats stats; /* linux 'netstat -i' statistics */
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int Index; /* internal board index number */
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/* adapter RAM sizes for queues of active port */
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int RxQueueSize; /* memory used for receive queue */
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int TxSQueueSize; /* memory used for sync. tx queue */
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int TxAQueueSize; /* memory used for async. tx queue */
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int PromiscCount; /* promiscuous mode counter */
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int AllMultiCount; /* allmulticast mode counter */
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int MulticCount; /* number of different MC */
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/* addresses for this board */
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/* (may be more than HW can)*/
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int HWRevision; /* Hardware revision */
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int ActivePort; /* the active XMAC port */
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int MaxPorts; /* number of activated ports */
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int TxDescrPerRing; /* # of descriptors per tx ring */
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int RxDescrPerRing; /* # of descriptors per rx ring */
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caddr_t pDescrMem; /* Pointer to the descriptor area */
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dma_addr_t pDescrMemDMA; /* PCI DMA address of area */
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/* the port structures with descriptor rings */
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TX_PORT TxPort[SK_MAX_MACS][2];
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RX_PORT RxPort[SK_MAX_MACS];
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unsigned int CsOfs1; /* for checksum calculation */
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unsigned int CsOfs2; /* for checksum calculation */
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SK_U32 CsOfs; /* for checksum calculation */
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SK_BOOL CheckQueue; /* check event queue soon */
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SK_TIMER DrvCleanupTimer;/* to check for pending descriptors */
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DIM_INFO DynIrqModInfo; /* all data related to DIM */
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/* Only for tests */
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int PortUp;
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int PortDown;
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int ChipsetType; /* Chipset family type
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* 0 == Genesis family support
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* 1 == Yukon family support
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*/
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#ifdef SK_DIAG_SUPPORT
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SK_U32 DiagModeActive; /* is diag active? */
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SK_BOOL DiagFlowCtrl; /* for control purposes */
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SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for all Pnmi-Data */
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SK_BOOL WasIfUp[SK_MAX_MACS]; /* for OpenClose while
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* DIAG is busy with NIC
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*/
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#endif
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};
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#endif /* __INC_SKDRV2ND_H */
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