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435 lines
14 KiB
435 lines
14 KiB
#ifndef __MYRI10GE_MCP_H__
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#define __MYRI10GE_MCP_H__
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#define MXGEFW_VERSION_MAJOR 1
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#define MXGEFW_VERSION_MINOR 4
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/* 8 Bytes */
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struct mcp_dma_addr {
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__be32 high;
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__be32 low;
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};
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/* 4 Bytes */
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struct mcp_slot {
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__sum16 checksum;
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__be16 length;
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};
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/* 64 Bytes */
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struct mcp_cmd {
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__be32 cmd;
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__be32 data0; /* will be low portion if data > 32 bits */
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/* 8 */
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__be32 data1; /* will be high portion if data > 32 bits */
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__be32 data2; /* currently unused.. */
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/* 16 */
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struct mcp_dma_addr response_addr;
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/* 24 */
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u8 pad[40];
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};
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/* 8 Bytes */
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struct mcp_cmd_response {
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__be32 data;
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__be32 result;
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};
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/*
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* flags used in mcp_kreq_ether_send_t:
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*
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* The SMALL flag is only needed in the first segment. It is raised
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* for packets that are total less or equal 512 bytes.
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*
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* The CKSUM flag must be set in all segments.
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*
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* The PADDED flags is set if the packet needs to be padded, and it
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* must be set for all segments.
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*
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* The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
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* length of all previous segments was odd.
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*/
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#define MXGEFW_FLAGS_SMALL 0x1
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#define MXGEFW_FLAGS_TSO_HDR 0x1
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#define MXGEFW_FLAGS_FIRST 0x2
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#define MXGEFW_FLAGS_ALIGN_ODD 0x4
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#define MXGEFW_FLAGS_CKSUM 0x8
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#define MXGEFW_FLAGS_TSO_LAST 0x8
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#define MXGEFW_FLAGS_NO_TSO 0x10
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#define MXGEFW_FLAGS_TSO_CHOP 0x10
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#define MXGEFW_FLAGS_TSO_PLD 0x20
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#define MXGEFW_SEND_SMALL_SIZE 1520
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#define MXGEFW_MAX_MTU 9400
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union mcp_pso_or_cumlen {
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u16 pseudo_hdr_offset;
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u16 cum_len;
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};
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#define MXGEFW_MAX_SEND_DESC 12
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#define MXGEFW_PAD 2
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/* 16 Bytes */
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struct mcp_kreq_ether_send {
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__be32 addr_high;
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__be32 addr_low;
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__be16 pseudo_hdr_offset;
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__be16 length;
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u8 pad;
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u8 rdma_count;
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u8 cksum_offset; /* where to start computing cksum */
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u8 flags; /* as defined above */
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};
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/* 8 Bytes */
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struct mcp_kreq_ether_recv {
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__be32 addr_high;
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__be32 addr_low;
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};
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/* Commands */
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#define MXGEFW_BOOT_HANDOFF 0xfc0000
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#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0
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#define MXGEFW_ETH_CMD 0xf80000
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#define MXGEFW_ETH_SEND_4 0x200000
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#define MXGEFW_ETH_SEND_1 0x240000
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#define MXGEFW_ETH_SEND_2 0x280000
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#define MXGEFW_ETH_SEND_3 0x2c0000
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#define MXGEFW_ETH_RECV_SMALL 0x300000
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#define MXGEFW_ETH_RECV_BIG 0x340000
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#define MXGEFW_ETH_SEND_GO 0x380000
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#define MXGEFW_ETH_SEND_STOP 0x3C0000
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#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000))
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#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
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enum myri10ge_mcp_cmd_type {
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MXGEFW_CMD_NONE = 0,
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/* Reset the mcp, it is left in a safe state, waiting
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* for the driver to set all its parameters */
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MXGEFW_CMD_RESET = 1,
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/* get the version number of the current firmware..
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* (may be available in the eeprom strings..? */
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MXGEFW_GET_MCP_VERSION = 2,
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/* Parameters which must be set by the driver before it can
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* issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
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* MXGEFW_CMD_RESET is issued */
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MXGEFW_CMD_SET_INTRQ_DMA = 3,
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/* data0 = LSW of the host address
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* data1 = MSW of the host address
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* data2 = slice number if multiple slices are used
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*/
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MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */
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MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */
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/* Parameters which refer to lanai SRAM addresses where the
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* driver must issue PIO writes for various things */
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MXGEFW_CMD_GET_SEND_OFFSET = 6,
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MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7,
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MXGEFW_CMD_GET_BIG_RX_OFFSET = 8,
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/* data0 = slice number if multiple slices are used */
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MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9,
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MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10,
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/* Parameters which refer to rings stored on the MCP,
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* and whose size is controlled by the mcp */
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MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */
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MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */
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/* Parameters which refer to rings stored in the host,
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* and whose size is controlled by the host. Note that
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* all must be physically contiguous and must contain
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* a power of 2 number of entries. */
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MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */
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#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31)
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/* command to bring ethernet interface up. Above parameters
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* (plus mtu & mac address) must have been exchanged prior
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* to issuing this command */
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MXGEFW_CMD_ETHERNET_UP = 14,
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/* command to bring ethernet interface down. No further sends
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* or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
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* is issued, and all interrupt queues must be flushed prior
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* to ack'ing this command */
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MXGEFW_CMD_ETHERNET_DOWN = 15,
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/* commands the driver may issue live, without resetting
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* the nic. Note that increasing the mtu "live" should
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* only be done if the driver has already supplied buffers
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* sufficiently large to handle the new mtu. Decreasing
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* the mtu live is safe */
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MXGEFW_CMD_SET_MTU = 16,
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MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */
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MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */
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MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */
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MXGEFW_ENABLE_PROMISC = 20,
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MXGEFW_DISABLE_PROMISC = 21,
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MXGEFW_SET_MAC_ADDRESS = 22,
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MXGEFW_ENABLE_FLOW_CONTROL = 23,
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MXGEFW_DISABLE_FLOW_CONTROL = 24,
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/* do a DMA test
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* data0,data1 = DMA address
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* data2 = RDMA length (MSH), WDMA length (LSH)
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* command return data = repetitions (MSH), 0.5-ms ticks (LSH)
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*/
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MXGEFW_DMA_TEST = 25,
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MXGEFW_ENABLE_ALLMULTI = 26,
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MXGEFW_DISABLE_ALLMULTI = 27,
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/* returns MXGEFW_CMD_ERROR_MULTICAST
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* if there is no room in the cache
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* data0,MSH(data1) = multicast group address */
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MXGEFW_JOIN_MULTICAST_GROUP = 28,
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/* returns MXGEFW_CMD_ERROR_MULTICAST
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* if the address is not in the cache,
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* or is equal to FF-FF-FF-FF-FF-FF
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* data0,MSH(data1) = multicast group address */
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MXGEFW_LEAVE_MULTICAST_GROUP = 29,
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MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30,
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MXGEFW_CMD_SET_STATS_DMA_V2 = 31,
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/* data0, data1 = bus addr,
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* data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
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* adding new stuff to mcp_irq_data without changing the ABI
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*
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* If multiple slices are used, data2 contains both the size of the
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* structure (in the lower 16 bits) and the slice number
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* (in the upper 16 bits).
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*/
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MXGEFW_CMD_UNALIGNED_TEST = 32,
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/* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
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* chipset */
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MXGEFW_CMD_UNALIGNED_STATUS = 33,
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/* return data = boolean, true if the chipset is known to be unaligned */
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MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34,
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/* data0 = number of big buffers to use. It must be 0 or a power of 2.
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* 0 indicates that the NIC consumes as many buffers as they are required
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* for packet. This is the default behavior.
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* A power of 2 number indicates that the NIC always uses the specified
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* number of buffers for each big receive packet.
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* It is up to the driver to ensure that this value is big enough for
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* the NIC to be able to receive maximum-sized packets.
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*/
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MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35,
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MXGEFW_CMD_ENABLE_RSS_QUEUES = 36,
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/* data0 = number of slices n (0, 1, ..., n-1) to enable
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* data1 = interrupt mode | use of multiple transmit queues.
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* 0=share one INTx/MSI.
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* 1=use one MSI-X per queue.
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* If all queues share one interrupt, the driver must have set
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* RSS_SHARED_INTERRUPT_DMA before enabling queues.
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* 2=enable both receive and send queues.
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* Without this bit set, only one send queue (slice 0's send queue)
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* is enabled. The receive queues are always enabled.
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*/
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#define MXGEFW_SLICE_INTR_MODE_SHARED 0x0
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#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1
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#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2
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MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37,
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MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38,
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/* data0, data1 = bus address lsw, msw */
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MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39,
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/* get the offset of the indirection table */
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MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40,
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/* set the size of the indirection table */
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MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41,
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/* get the offset of the secret key */
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MXGEFW_CMD_RSS_KEY_UPDATED = 42,
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/* tell nic that the secret key's been updated */
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MXGEFW_CMD_SET_RSS_ENABLE = 43,
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/* data0 = enable/disable rss
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* 0: disable rss. nic does not distribute receive packets.
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* 1: enable rss. nic distributes receive packets among queues.
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* data1 = hash type
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* 1: IPV4 (required by RSS)
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* 2: TCP_IPV4 (required by RSS)
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* 3: IPV4 | TCP_IPV4 (required by RSS)
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* 4: source port
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* 5: source port + destination port
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*/
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#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1
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#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2
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#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4
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#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5
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#define MXGEFW_RSS_HASH_TYPE_MAX 0x5
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MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44,
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/* Return data = the max. size of the entire headers of a IPv6 TSO packet.
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* If the header size of a IPv6 TSO packet is larger than the specified
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* value, then the driver must not use TSO.
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* This size restriction only applies to IPv6 TSO.
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* For IPv4 TSO, the maximum size of the headers is fixed, and the NIC
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* always has enough header buffer to store maximum-sized headers.
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*/
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MXGEFW_CMD_SET_TSO_MODE = 45,
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/* data0 = TSO mode.
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* 0: Linux/FreeBSD style (NIC default)
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* 1: NDIS/NetBSD style
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*/
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#define MXGEFW_TSO_MODE_LINUX 0
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#define MXGEFW_TSO_MODE_NDIS 1
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MXGEFW_CMD_MDIO_READ = 46,
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/* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
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MXGEFW_CMD_MDIO_WRITE = 47,
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/* data0 = dev_addr, data1 = register/addr, data2 = value */
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MXGEFW_CMD_I2C_READ = 48,
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/* Starts to get a fresh copy of one byte or of the module i2c table, the
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* obtained data is cached inside the xaui-xfi chip :
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* data0 : 0 => get one byte, 1=> get 256 bytes
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* data1 : If data0 == 0: location to refresh
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* bit 7:0 register location
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* bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1)
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* bit 23:16 is the i2c bus number (for multi-port NICs)
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* If data0 == 1: unused
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* The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes
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* During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts
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* will return MXGEFW_CMD_ERROR_BUSY
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*/
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MXGEFW_CMD_I2C_BYTE = 49,
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/* Return the last obtained copy of a given byte in the xfp i2c table
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* (copy cached during the last relevant MXGEFW_CMD_I2C_READ)
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* data0 : index of the desired table entry
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* Return data = the byte stored at the requested index in the table
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*/
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MXGEFW_CMD_GET_VPUMP_OFFSET = 50,
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/* Return data = NIC memory offset of mcp_vpump_public_global */
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MXGEFW_CMD_RESET_VPUMP = 51,
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/* Resets the VPUMP state */
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MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52,
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/* data0 = mcp_slot type to use.
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* 0 = the default 4B mcp_slot
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* 1 = 8B mcp_slot_8
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*/
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#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0
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#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1
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MXGEFW_CMD_SET_THROTTLE_FACTOR = 53,
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/* set the throttle factor for ethp_z8e
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* data0 = throttle_factor
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* throttle_factor = 256 * pcie-raw-speed / tx_speed
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* tx_speed = 256 * pcie-raw-speed / throttle_factor
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*
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* For PCI-E x8: pcie-raw-speed == 16Gb/s
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* For PCI-E x4: pcie-raw-speed == 8Gb/s
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*
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* ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s
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* ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s
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*
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* with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s
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* with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
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*/
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MXGEFW_CMD_VPUMP_UP = 54,
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/* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
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MXGEFW_CMD_GET_VPUMP_CLK = 55,
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/* Get the lanai clock */
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MXGEFW_CMD_GET_DCA_OFFSET = 56,
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/* offset of dca control for WDMAs */
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/* VMWare NetQueue commands */
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MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57,
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MXGEFW_CMD_NETQ_ADD_FILTER = 58,
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/* data0 = filter_id << 16 | queue << 8 | type */
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/* data1 = MS4 of MAC Addr */
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/* data2 = LS2_MAC << 16 | VLAN_tag */
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MXGEFW_CMD_NETQ_DEL_FILTER = 59,
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/* data0 = filter_id */
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MXGEFW_CMD_NETQ_QUERY1 = 60,
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MXGEFW_CMD_NETQ_QUERY2 = 61,
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MXGEFW_CMD_NETQ_QUERY3 = 62,
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MXGEFW_CMD_NETQ_QUERY4 = 63,
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MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64,
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/* When set, small receive buffers can cross page boundaries.
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* Both small and big receive buffers may start at any address.
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* This option has performance implications, so use with caution.
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*/
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};
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enum myri10ge_mcp_cmd_status {
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MXGEFW_CMD_OK = 0,
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MXGEFW_CMD_UNKNOWN = 1,
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MXGEFW_CMD_ERROR_RANGE = 2,
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MXGEFW_CMD_ERROR_BUSY = 3,
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MXGEFW_CMD_ERROR_EMPTY = 4,
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MXGEFW_CMD_ERROR_CLOSED = 5,
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MXGEFW_CMD_ERROR_HASH_ERROR = 6,
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MXGEFW_CMD_ERROR_BAD_PORT = 7,
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MXGEFW_CMD_ERROR_RESOURCES = 8,
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MXGEFW_CMD_ERROR_MULTICAST = 9,
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MXGEFW_CMD_ERROR_UNALIGNED = 10,
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MXGEFW_CMD_ERROR_NO_MDIO = 11,
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MXGEFW_CMD_ERROR_I2C_FAILURE = 12,
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MXGEFW_CMD_ERROR_I2C_ABSENT = 13,
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MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14
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};
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#define MXGEFW_OLD_IRQ_DATA_LEN 40
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struct mcp_irq_data {
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/* add new counters at the beginning */
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__be32 future_use[1];
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__be32 dropped_pause;
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__be32 dropped_unicast_filtered;
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__be32 dropped_bad_crc32;
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__be32 dropped_bad_phy;
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__be32 dropped_multicast_filtered;
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/* 40 Bytes */
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__be32 send_done_count;
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#define MXGEFW_LINK_DOWN 0
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#define MXGEFW_LINK_UP 1
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#define MXGEFW_LINK_MYRINET 2
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#define MXGEFW_LINK_UNKNOWN 3
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__be32 link_up;
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__be32 dropped_link_overflow;
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__be32 dropped_link_error_or_filtered;
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__be32 dropped_runt;
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__be32 dropped_overrun;
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__be32 dropped_no_small_buffer;
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__be32 dropped_no_big_buffer;
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__be32 rdma_tags_available;
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u8 tx_stopped;
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u8 link_down;
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u8 stats_updated;
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u8 valid;
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};
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/* definitions for NETQ filter type */
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#define MXGEFW_NETQ_FILTERTYPE_NONE 0
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#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1
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#define MXGEFW_NETQ_FILTERTYPE_VLAN 2
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#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3
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#endif /* __MYRI10GE_MCP_H__ */
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