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332 lines
13 KiB
332 lines
13 KiB
MSM PCIe
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MSM PCI express root complex
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Required properties:
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- compatible: should be "qcom,pci-msm"
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- cell-index: defines root complex ID.
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- #address-cells: Should provide a value of 0.
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- reg: should contain PCIe register maps.
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- reg-names: indicates various resources passed to driver by name.
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Should be "parf", "phy", "dm_core", "elbi", "conf", "io", "bars".
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These correspond to different modules within the PCIe core.
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- ranges: For details of ranges properties, please refer to:
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"Documentation\devicetree\bindings\pci\pci.txt"
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- interrupts: Should be in the format <0 1 2> and it is an index to the
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interrupt-map that contains PCIe related interrupts.
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- #interrupt-cells: Should provide a value of 1.
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- #interrupt-map-mask: should provide a value of 0xffffffff.
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- interrupt-map: Must create mapping for the number of interrupts
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that are defined in above interrupts property.
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For PCIe device node, it should define 12 mappings for
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the corresponding PCIe interrupts supporting the specification.
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- interrupt-names: indicates interrupts passed to driver by name.
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Should be "int_a", "int_b", "int_c", "int_d",
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"int_pls_pme", "int_pme_legacy", "int_pls_err",
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"int_aer_legacy", "int_pls_link_up",
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"int_pls_link_down", "int_bridge_flush_n"
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These correspond to the standard PCIe specification to support
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virtual IRQ's (INT#), link state notifications.
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- perst-gpio: PERST GPIO specified by PCIe spec.
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- wake-gpio: WAKE GPIO specified by PCIe spec.
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- phy-status-offset: Offset from PCIe PHY base to check if PCIe PHY is up.
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- phy-status-bit: BIT to check PCIe PHY status.
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- pcie_rc<PCIe index>: PCI node is a sub-node of PCIe controller node.
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node. This node holds root complex specific configurations and properties.
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- <supply-name>-supply: phandle to the regulator device tree node.
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Refer to the schematics for the corresponding voltage regulators.
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vreg-1.8-supply: phandle to the analog supply for the PCIe controller.
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vreg-3.3-supply: phandle to the analog supply for the PCIe controller.
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vreg-0.9-supply: phandle to the analog supply for the PCIe controller.
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Optional Properties:
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- qcom,<supply-name>-voltage-level: specifies voltage levels for supply.
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Should be specified in pairs (max, min, optimal), units uV.
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- clkreq-gpio: CLKREQ GPIO specified by PCIe spec.
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- qcom,ep-gpio: GPIO which enables a certain type of endpoint for link training.
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- pinctrl-names: The state name of the pin configuration.
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supports: "default", "sleep"
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- pinctrl-0: For details of pinctrl properties, please refer to:
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"Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt"
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- pinctrl-1: For details of pinctrl properties, please refer to:
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"Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt"
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- clocks: list of clock phandles
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- clock-names: list of names of clock inputs.
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Should be "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo";
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- max-clock-frequency-hz: list of the maximum operating frequencies stored
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in the same order of clock names;
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- qcom,no-l0s-supported: L0s is not supported.
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- qcom,no-l1-supported: L1 is not supported.
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- qcom,no-l1ss-supported: L1 sub-states (L1ss) is not supported.
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- qcom,no-aux-clk-sync: The AUX clock is not synchronous to the Core clock to
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support L1ss.
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- qcom,common-clk-en: Enables the common clock configuration for the endpoint.
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- qcom,clk-power-manage-en: Enables the clock power management for the
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endpoint.
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- qcom,target-link-speed: Override maximum GEN speed.
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GEN 1: 0x1
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GEN 2: 0x2
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GEN 3: 0x3
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- qcom,n-fts: The number of fast training sequences sent when the link state
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is changed from L0s to L0.
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- qcom,phy-power-down-offset: Offset from PCIe PHY base to control the power state
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of the PHY.
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- qcom,core-preset: Value for PCIe core preset. Determines how aggressive the
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PCIe PHY equalization is. The following are recommended settings:
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short channels: 0x55555555 (default)
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long channels: 0x77777777
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- qcom,pcie-phy-ver: version of PCIe PHY.
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- qcom,phy-sequence: The initialization sequence to bring up the PCIe PHY.
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Should be specified in groups (offset, value, delay).
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Should be specified in groups (offset, value, delay).
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- qcom,bw-scale: Table of CX voltage and rate change clock frequency pair
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for PCIe bandwidth scaling.
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- qcom,use-19p2mhz-aux-clk: The frequency of PCIe AUX clock is 19.2MHz.
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- qcom,boot-option: Bits that alter PCIe bus driver boot sequence.
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Below details what happens when each bit is set
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BIT(0): PCIe bus driver will not start enumeration during its probe.
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Clients will control when PCIe bus driver should do enumeration.
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BIT(1): PCIe bus driver will not start enumeration if it receives a WAKE
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interrupt.
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- qcom,ext-ref-clk: The reference clock is external.
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- iommu-map: For details of iommu-map properties, please refer to:
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"Documentation/devicetree/bindings/pci/pci-iommu.txt"
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- iommus: the phandle and stream IDs for the SMMU used by this root
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complex. This should be used in separate nodes from the main root
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complex nodes, and is the only property needed in that case.
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- qcom,smmu-sid-base: The base SMMU SID that PCIe bus driver will use to calculate
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and assign for each endpoint.
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- qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become
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stable after power on, before de-assert the PERST to the endpoint.
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- qcom,switch-latency: The time (unit: ms) to wait for the PCIe endpoint's link
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training with switch downstream port after the link between switch upstream
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port and RC is up.
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- qcom,wr-halt-size: With base 2, this exponent determines the size of the
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data that PCIe core will halt on for each write transaction.
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- qcom,slv-addr-space-size: The memory space size of PCIe Root Complex.
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- qcom,cpl-timeout: Completion timeout value. This value specifies the time range
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which the root complex will send out a completion packet if there is no response
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from the endpoint.
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- linux,pci-domain: For details of pci-domains properties, please refer to:
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"Documentation/devicetree/bindings/pci/pci.txt"
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- qcom,perst-delay-us-min: The minimum allowed time (unit: us) to sleep after
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asserting or de-asserting PERST GPIO.
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- qcom,perst-delay-us-max: The maximum allowed time (unit: us) to sleep after
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asserting or de-asserting PERST GPIO.
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- qcom,tlp-rd-size: The max TLP read size (Calculation: 128 times 2 to the
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tlp-rd-size power).
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- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
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below optional properties:
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- qcom,msm-bus,name
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- qcom,msm-bus,num-cases
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- qcom,msm-bus,num-paths
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- qcom,msm-bus,vectors-KBps
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- resets: reset specifier pair consists of phandle for the reset controller
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and reset lines used by this controller.
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- reset-names: reset signal name strings sorted in the same order as the resets
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property.
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- clock-output-names: name of the outgoing clock signal from the PHY PLL.
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- qcom,keep-powerdown-phy: If present, power down phy in probe to avoid leakage.
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- errata: Selects the list of erratas to configure for the
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corresponding switch port. This could be a third party switch connected to
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the root port.
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=================
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Root Complex node
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=================
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Root complex are defined as subnodes of the PCIe controller node.
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Required properties:
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- reg: Array (5-cell PCI resource) of <u32>. First cell is devfn, which is
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determined by pci bus topology. Assign the other cells 0 since they are not
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used.
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Optional properties:
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- qcom,iommu-cfg: Determines whether PCIe bus driver is required to configure
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SMMU that sits behind the PCIe controller.
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Bit mask:
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BIT(0) : Indicates if SMMU is present
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BIT(1) : Set IOMMU attribute S1_BYPASS
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BIT(2) : Set IOMMU attribute FAST
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BIT(3) : Set IOMMU attribute ATOMIC
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BIT(4) : Set IOMMU attribute FORCE COHERENT
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- qcom,iommu-range: Pair of values describing iova base and size to allocate.
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Example:
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pcie0: qcom,pcie@fc520000 {
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compatible = "qcom,msm_pcie";
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cell-index = <0>;
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#address-cells = <0>;
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reg = <0xfc520000 0x2000>,
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<0xfc526000 0x1000>,
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<0xff000000 0x1000>,
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<0xff001000 0x1000>,
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<0xff100000 0x1000>,
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<0xff200000 0x100000>,
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<0xff300000 0xd00000>;
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reg-names = "parf", "dm_core", "elbi",
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"conf", "io", "bars";
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ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
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<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4 5 6 7 8 9 10 11
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12 13 14 15 16 17 18 19 20
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21 22 23 24 25 26 27 28 29
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30 31 32 33 34 35 36 37 38
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39 40 41 42 43>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0x0 0x0 0x0 0 &intc 0 405 0
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0x0 0x0 0x0 1 &intc 0 244 0
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0x0 0x0 0x0 2 &intc 0 245 0
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0x0 0x0 0x0 3 &intc 0 247 0
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0x0 0x0 0x0 4 &intc 0 248 0
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0x0 0x0 0x0 5 &intc 0 249 0
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0x0 0x0 0x0 6 &intc 0 250 0
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0x0 0x0 0x0 7 &intc 0 251 0
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0x0 0x0 0x0 8 &intc 0 252 0
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0x0 0x0 0x0 9 &intc 0 253 0
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0x0 0x0 0x0 10 &intc 0 254 0
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0x0 0x0 0x0 11 &intc 0 255 0
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0x0 0x0 0x0 12 &intc 0 448 0
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0x0 0x0 0x0 13 &intc 0 449 0
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0x0 0x0 0x0 14 &intc 0 450 0
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0x0 0x0 0x0 15 &intc 0 451 0
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0x0 0x0 0x0 16 &intc 0 452 0
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0x0 0x0 0x0 17 &intc 0 453 0
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0x0 0x0 0x0 18 &intc 0 454 0
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0x0 0x0 0x0 19 &intc 0 455 0
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0x0 0x0 0x0 20 &intc 0 456 0
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0x0 0x0 0x0 21 &intc 0 457 0
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0x0 0x0 0x0 22 &intc 0 458 0
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0x0 0x0 0x0 23 &intc 0 459 0
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0x0 0x0 0x0 24 &intc 0 460 0
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0x0 0x0 0x0 25 &intc 0 461 0
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0x0 0x0 0x0 26 &intc 0 462 0
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0x0 0x0 0x0 27 &intc 0 463 0
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0x0 0x0 0x0 28 &intc 0 464 0
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0x0 0x0 0x0 29 &intc 0 465 0
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0x0 0x0 0x0 30 &intc 0 466 0
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0x0 0x0 0x0 31 &intc 0 467 0
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0x0 0x0 0x0 32 &intc 0 468 0
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0x0 0x0 0x0 33 &intc 0 469 0
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0x0 0x0 0x0 34 &intc 0 470 0
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0x0 0x0 0x0 35 &intc 0 471 0
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0x0 0x0 0x0 36 &intc 0 472 0
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0x0 0x0 0x0 37 &intc 0 473 0
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0x0 0x0 0x0 38 &intc 0 474 0
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0x0 0x0 0x0 39 &intc 0 475 0
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0x0 0x0 0x0 40 &intc 0 476 0
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0x0 0x0 0x0 41 &intc 0 477 0
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0x0 0x0 0x0 42 &intc 0 478 0
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0x0 0x0 0x0 43 &intc 0 479 0>;
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interrupt-names = int_a", "int_b", "int_c", "int_d",
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"int_pls_pme", "int_pme_legacy", "int_pls_err",
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"int_aer_legacy", "int_pls_link_up",
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"int_pls_link_down", "int_bridge_flush_n";
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qcom,phy-sequence = <0x804 0x01 0x00
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0x034 0x14 0x00
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0x138 0x30 0x00
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0x048 0x0f 0x00
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0x15c 0x06 0x00
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0x090 0x01 0x00
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0x808 0x03 0x00>;
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perst-gpio = <&msmgpio 70 0>;
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wake-gpio = <&msmgpio 69 0>;
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clkreq-gpio = <&msmgpio 68 0>;
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qcom,ep-gpio = <&tlmm 94 0>;
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gdsc-vdd-supply = <&gdsc_pcie_0>;
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vreg-1.8-supply = <&pma8084_l12>;
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vreg-0.9-supply = <&pma8084_l4>;
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vreg-3.3-supply = <&wlan_vreg>;
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qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;
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qcom,vreg-0.9-voltage-level = <950000 950000 24000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
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pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_sleep &pcie0_wake_sleep>;
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clocks = <&clock_gcc clk_gcc_pcie_0_pipe_clk>,
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<&clock_rpm clk_ln_bb_clk>,
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<&clock_gcc clk_gcc_pcie_0_aux_clk>,
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<&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>,
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<&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>,
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<&clock_gcc clk_gcc_pcie_0_slv_axi_clk>,
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<&clock_gcc clk_pcie_0_phy_ldo>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo";
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resets = <&clock_gcc GCC_PCIE_PHY_BCR>,
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<&clock_gcc GCC_PCIE_PHY_COM_BCR>,
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<&clock_gcc GCC_PCIE_PHY_NOCSR_COM_PHY_BCR>,
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<&clock_gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_phy_reset", "pcie_phy_com_reset",
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"pcie_phy_nocsr_com_phy_reset","pcie_0_phy_reset";
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max-clock-frequency-hz = <125000000>, <0>, <1000000>,
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<0>, <0>, <0>, <0>;
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qcom,no-l0s-supported;
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qcom,no-l1-supported;
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qcom,no-l1ss-supported;
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qcom,no-aux-clk-sync;
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qcom,target-link-speed = <0x2>;
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qcom,n-fts = <0x50>;
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qcom,pcie-phy-ver = <1>;
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qcom,boot-option = <0x1>;
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qcom,ext-ref-clk;
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qcom,tlp-rd-size = <0x5>;
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qcom,smmu-sid-base = <0x1480>;
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qcom,ep-latency = <100>;
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qcom,switch-latency = <100>;
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qcom,wr-halt-size = <0xa>; /* 1KB */
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qcom,slv-addr-space-size = <0x1000000>; /* 16MB */
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qcom,phy-status-offset = <0x800>;
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qcom,phy-status-status = <6>;
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qcom,phy-power-down-offset = <0x840>;
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qcom,core-preset = <0x55555555>; /* short channels */
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qcom,cpl-timeout = <0x2>;
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iommus = <&anoc0_smmu>;
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iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
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<0x100 &apps_smmu 0x1d81 0x1>,
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<0x200 &apps_smmu 0x1d82 0x1>,
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<0x300 &apps_smmu 0x1d83 0x1>,
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<0x400 &apps_smmu 0x1d84 0x1>,
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<0x500 &apps_smmu 0x1d85 0x1>,
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<0x600 &apps_smmu 0x1d86 0x1>,
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<0x700 &apps_smmu 0x1d87 0x1>,
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<0x800 &apps_smmu 0x1d88 0x1>,
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<0x900 &apps_smmu 0x1d89 0x1>,
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<0xa00 &apps_smmu 0x1d8a 0x1>,
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<0xb00 &apps_smmu 0x1d8b 0x1>,
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<0xc00 &apps_smmu 0x1d8c 0x1>,
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<0xd00 &apps_smmu 0x1d8d 0x1>,
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<0xe00 &apps_smmu 0x1d8e 0x1>,
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<0xf00 &apps_smmu 0x1d8f 0x1>;
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qcom,msm-bus,name = "pcie0";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<45 512 0 0>,
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<45 512 500 800>;
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pcie_rc0: pcie_rc0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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qcom,iommu-cfg = <0x3> /* SMMU PRESENT. SET S1 BYPASS */
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qcom,iommu-range = <0x0 0x10000000 0x0 0x40000000>;
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};
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};
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