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#ifndef _NM256_H_
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#define _NM256_H_
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include "ac97.h"
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/* The revisions that we currently handle. */
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enum nm256rev {
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REV_NM256AV, REV_NM256ZX
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};
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/* Per-card structure. */
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struct nm256_info
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{
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/* Magic number used to verify that this struct is valid. */
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#define NM_MAGIC_SIG 0x55aa00ff
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int magsig;
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/* Revision number */
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enum nm256rev rev;
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struct ac97_hwint mdev;
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/* Our audio device numbers. */
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int dev[2];
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/* The # of times each device has been opened. (Should only be
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0 or 1). */
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int opencnt[2];
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/* We use two devices, because we can do simultaneous play and record.
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This keeps track of which device is being used for what purpose;
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these are the actual device numbers. */
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int dev_for_play;
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int dev_for_record;
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spinlock_t lock;
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/* The mixer device. */
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int mixer_oss_dev;
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/*
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* Can only be opened once for each operation. These aren't set
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* until an actual I/O operation is performed; this allows one
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* device to be open for read/write without inhibiting I/O to
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* the other device.
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*/
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int is_open_play;
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int is_open_record;
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/* Non-zero if we're currently playing a sample. */
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int playing;
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/* Ditto for recording a sample. */
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int recording;
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/* The two memory ports. */
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struct nm256_ports {
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/* Physical address of the port. */
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u32 physaddr;
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/* Our mapped-in pointer. */
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char __iomem *ptr;
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/* PTR's offset within the physical port. */
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u32 start_offset;
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/* And the offset of the end of the buffer. */
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u32 end_offset;
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} port[2];
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/* The following are offsets within memory port 1. */
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u32 coeffBuf;
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u32 allCoeffBuf;
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/* Record and playback buffers. */
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u32 abuf1, abuf2;
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/* Offset of the AC97 mixer in memory port 2. */
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u32 mixer;
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/* Offset of the mixer status register in memory port 2. */
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u32 mixer_status_offset;
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/* Non-zero if we have written initial values to the mixer. */
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u8 mixer_values_init;
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/*
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* Status mask bit; (*mixer_status_loc & mixer_status_mask) == 0 means
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* it's ready.
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*/
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u16 mixer_status_mask;
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/* The sizes of the playback and record ring buffers. */
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u32 playbackBufferSize;
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u32 recordBufferSize;
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/* Are the coefficient values in the memory cache current? */
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u8 coeffsCurrent;
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/* For writes, the amount we last wrote. */
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u32 requested_amt;
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/* The start of the block currently playing. */
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u32 curPlayPos;
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/* The amount of data we were requested to record. */
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u32 requestedRecAmt;
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/* The offset of the currently-recording block. */
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u32 curRecPos;
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/* The destination buffer. */
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char *recBuf;
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/* Our IRQ number. */
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int irq;
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/* A flag indicating how many times we've grabbed the IRQ. */
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int has_irq;
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/* The card interrupt service routine. */
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irqreturn_t (*introutine) (int, void *, struct pt_regs *);
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/* Current audio config, cached. */
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struct sinfo {
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u32 samplerate;
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u8 bits;
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u8 stereo;
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} sinfo[2]; /* goes with each device */
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/* The cards are stored in a chain; this is the next card. */
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struct nm256_info *next_card;
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};
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/* The BIOS signature. */
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#define NM_SIGNATURE 0x4e4d0000
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/* Signature mask. */
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#define NM_SIG_MASK 0xffff0000
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/* Size of the second memory area. */
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#define NM_PORT2_SIZE 4096
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/* The base offset of the mixer in the second memory area. */
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#define NM_MIXER_OFFSET 0x600
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/* The maximum size of a coefficient entry. */
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#define NM_MAX_COEFFICIENT 0x5000
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/* The interrupt register. */
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#define NM_INT_REG 0xa04
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/* And its bits. */
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#define NM_PLAYBACK_INT 0x40
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#define NM_RECORD_INT 0x100
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#define NM_MISC_INT_1 0x4000
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#define NM_MISC_INT_2 0x1
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#define NM_ACK_INT(CARD, X) nm256_writePort16((CARD), 2, NM_INT_REG, (X) << 1)
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/* The AV's "mixer ready" status bit and location. */
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#define NM_MIXER_STATUS_OFFSET 0xa04
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#define NM_MIXER_READY_MASK 0x0800
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#define NM_MIXER_PRESENCE 0xa06
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#define NM_PRESENCE_MASK 0x0050
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#define NM_PRESENCE_VALUE 0x0040
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/*
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* For the ZX. It uses the same interrupt register, but it holds 32
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* bits instead of 16.
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*/
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#define NM2_PLAYBACK_INT 0x10000
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#define NM2_RECORD_INT 0x80000
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#define NM2_MISC_INT_1 0x8
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#define NM2_MISC_INT_2 0x2
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#define NM2_ACK_INT(CARD, X) nm256_writePort32((CARD), 2, NM_INT_REG, (X))
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/* The ZX's "mixer ready" status bit and location. */
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#define NM2_MIXER_STATUS_OFFSET 0xa06
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#define NM2_MIXER_READY_MASK 0x0800
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/* The playback registers start from here. */
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#define NM_PLAYBACK_REG_OFFSET 0x0
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/* The record registers start from here. */
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#define NM_RECORD_REG_OFFSET 0x200
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/* The rate register is located 2 bytes from the start of the register area. */
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#define NM_RATE_REG_OFFSET 2
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/* Mono/stereo flag, number of bits on playback, and rate mask. */
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#define NM_RATE_STEREO 1
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#define NM_RATE_BITS_16 2
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#define NM_RATE_MASK 0xf0
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/* Playback enable register. */
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#define NM_PLAYBACK_ENABLE_REG (NM_PLAYBACK_REG_OFFSET + 0x1)
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#define NM_PLAYBACK_ENABLE_FLAG 1
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#define NM_PLAYBACK_ONESHOT 2
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#define NM_PLAYBACK_FREERUN 4
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/* Mutes the audio output. */
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#define NM_AUDIO_MUTE_REG (NM_PLAYBACK_REG_OFFSET + 0x18)
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#define NM_AUDIO_MUTE_LEFT 0x8000
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#define NM_AUDIO_MUTE_RIGHT 0x0080
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/* Recording enable register. */
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#define NM_RECORD_ENABLE_REG (NM_RECORD_REG_OFFSET + 0)
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#define NM_RECORD_ENABLE_FLAG 1
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#define NM_RECORD_FREERUN 2
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#define NM_RBUFFER_START (NM_RECORD_REG_OFFSET + 0x4)
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#define NM_RBUFFER_END (NM_RECORD_REG_OFFSET + 0x10)
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#define NM_RBUFFER_WMARK (NM_RECORD_REG_OFFSET + 0xc)
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#define NM_RBUFFER_CURRP (NM_RECORD_REG_OFFSET + 0x8)
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#define NM_PBUFFER_START (NM_PLAYBACK_REG_OFFSET + 0x4)
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#define NM_PBUFFER_END (NM_PLAYBACK_REG_OFFSET + 0x14)
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#define NM_PBUFFER_WMARK (NM_PLAYBACK_REG_OFFSET + 0xc)
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#define NM_PBUFFER_CURRP (NM_PLAYBACK_REG_OFFSET + 0x8)
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/* A few trivial routines to make it easier to work with the registers
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on the chip. */
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/* This is a common code portion used to fix up the port offsets. */
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#define NM_FIX_PORT \
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if (port < 1 || port > 2 || card == NULL) \
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return -1; \
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\
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if (offset < card->port[port - 1].start_offset \
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|| offset >= card->port[port - 1].end_offset) { \
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printk (KERN_ERR "Bad access: port %d, offset 0x%x\n", port, offset); \
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return -1; \
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} \
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offset -= card->port[port - 1].start_offset;
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#define DEFwritePortX(X, func) \
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static inline int nm256_writePort##X (struct nm256_info *card,\
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int port, int offset, int value)\
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{\
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u##X __iomem *addr;\
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\
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if (nm256_debug > 1)\
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printk (KERN_DEBUG "Writing 0x%x to %d:0x%x\n", value, port, offset);\
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\
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NM_FIX_PORT;\
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\
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addr = (u##X __iomem *)(card->port[port - 1].ptr + offset);\
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func (value, addr);\
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return 0;\
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}
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DEFwritePortX (8, writeb)
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DEFwritePortX (16, writew)
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DEFwritePortX (32, writel)
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#define DEFreadPortX(X, func) \
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static inline u##X nm256_readPort##X (struct nm256_info *card,\
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int port, int offset)\
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{\
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u##X __iomem *addr;\
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\
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NM_FIX_PORT\
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\
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addr = (u##X __iomem *)(card->port[port - 1].ptr + offset);\
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return func(addr);\
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}
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DEFreadPortX (8, readb)
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DEFreadPortX (16, readw)
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DEFreadPortX (32, readl)
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static inline int
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nm256_writeBuffer8 (struct nm256_info *card, u8 *src, int port, int offset,
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int amt)
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{
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NM_FIX_PORT;
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memcpy_toio (card->port[port - 1].ptr + offset, src, amt);
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return 0;
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}
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static inline int
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nm256_readBuffer8 (struct nm256_info *card, u8 *dst, int port, int offset,
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int amt)
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{
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NM_FIX_PORT;
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memcpy_fromio (dst, card->port[port - 1].ptr + offset, amt);
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return 0;
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}
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/* Returns a non-zero value if we should use the coefficient cache. */
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static int nm256_cachedCoefficients (struct nm256_info *card);
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#endif
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/*
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* Local variables:
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* c-basic-offset: 4
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* End:
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*/
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