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97 lines
3.6 KiB
97 lines
3.6 KiB
/*
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* include/asm-v850/gbus_int.h -- Midas labs GBUS interrupt support
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*
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* Copyright (C) 2001,02 NEC Corporation
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* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_GBUS_INT_H__
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#define __V850_GBUS_INT_H__
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/* The GBUS interrupt interface has 32 interrupts shared among 4
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processor interrupts. The 32 GBUS interrupts are divided into two
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sets of 16 each, for allocating among control registers, etc (there
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are two of each control register, with bits 0-15 controlling an
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interrupt each). */
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/* The GBUS interrupts themselves. */
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#define IRQ_GBUS_INT(n) (GBUS_INT_BASE_IRQ + (n))
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#define IRQ_GBUS_INT_NUM 32
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/* Control registers. */
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#define GBUS_INT_STATUS_ADDR(w) (GBUS_INT_BASE_ADDR + (w)*0x40)
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#define GBUS_INT_STATUS(w) (*(volatile u16 *)GBUS_INT_STATUS_ADDR(w))
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#define GBUS_INT_CLEAR_ADDR(w) (GBUS_INT_BASE_ADDR + 0x10 + (w)*0x40)
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#define GBUS_INT_CLEAR(w) (*(volatile u16 *)GBUS_INT_CLEAR_ADDR(w))
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#define GBUS_INT_EDGE_ADDR(w) (GBUS_INT_BASE_ADDR + 0x20 + (w)*0x40)
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#define GBUS_INT_EDGE(w) (*(volatile u16 *)GBUS_INT_EDGE_ADDR(w))
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#define GBUS_INT_POLARITY_ADDR(w) (GBUS_INT_BASE_ADDR + 0x30 + (w)*0x40)
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#define GBUS_INT_POLARITY(w) (*(volatile u16 *)GBUS_INT_POLARITY_ADDR(w))
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/* This allows enabling interrupt bits in word W for interrupt GINTn. */
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#define GBUS_INT_ENABLE_ADDR(w, n) \
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(GBUS_INT_BASE_ADDR + 0x100 + (w)*0x10 + (n)*0x20)
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#define GBUS_INT_ENABLE(w, n) (*(volatile u16 *)GBUS_INT_ENABLE_ADDR(w, n))
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/* Mapping between kernel interrupt numbers and hardware control regs/bits. */
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#define GBUS_INT_BITS_PER_WORD 16
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#define GBUS_INT_NUM_WORDS (IRQ_GBUS_INT_NUM / GBUS_INT_BITS_PER_WORD)
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#define GBUS_INT_IRQ_WORD(irq) (((irq) - GBUS_INT_BASE_IRQ) >> 4)
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#define GBUS_INT_IRQ_BIT(irq) (((irq) - GBUS_INT_BASE_IRQ) & 0xF)
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#define GBUS_INT_IRQ_MASK(irq) (1 << GBUS_INT_IRQ_BIT(irq))
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/* Possible priorities for GBUS interrupts. */
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#define GBUS_INT_PRIORITY_HIGH 2
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#define GBUS_INT_PRIORITY_MEDIUM 4
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#define GBUS_INT_PRIORITY_LOW 6
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#ifndef __ASSEMBLY__
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/* Enable interrupt handling for interrupt IRQ. */
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extern void gbus_int_enable_irq (unsigned irq);
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/* Disable interrupt handling for interrupt IRQ. Note that any
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interrupts received while disabled will be delivered once the
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interrupt is enabled again, unless they are explicitly cleared using
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`gbus_int_clear_pending_irq'. */
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extern void gbus_int_disable_irq (unsigned irq);
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/* Return true if interrupt handling for interrupt IRQ is enabled. */
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extern int gbus_int_irq_enabled (unsigned irq);
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/* Disable all GBUS irqs. */
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extern void gbus_int_disable_irqs (void);
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/* Clear any pending interrupts for IRQ. */
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extern void gbus_int_clear_pending_irq (unsigned irq);
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/* Return true if interrupt IRQ is pending (but disabled). */
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extern int gbus_int_irq_pending (unsigned irq);
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struct gbus_int_irq_init {
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const char *name; /* name of interrupt type */
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/* Range of kernel irq numbers for this type:
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BASE, BASE+INTERVAL, ..., BASE+INTERVAL*NUM */
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unsigned base, num, interval;
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unsigned priority; /* interrupt priority to assign */
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};
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struct hw_interrupt_type; /* fwd decl */
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/* Initialize HW_IRQ_TYPES for GBUS irqs described in array
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INITS (which is terminated by an entry with the name field == 0). */
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extern void gbus_int_init_irq_types (struct gbus_int_irq_init *inits,
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struct hw_interrupt_type *hw_irq_types);
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/* Initialize GBUS interrupts. */
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extern void gbus_int_init_irqs (void);
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#endif /* !__ASSEMBLY__ */
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#endif /* __V850_GBUS_INT_H__ */
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