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379 lines
11 KiB
379 lines
11 KiB
#ifndef _SMU_H
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#define _SMU_H
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/*
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* Definitions for talking to the SMU chip in newer G5 PowerMacs
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*/
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#include <linux/config.h>
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#include <linux/list.h>
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/*
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* Known SMU commands
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*
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* Most of what is below comes from looking at the Open Firmware driver,
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* though this is still incomplete and could use better documentation here
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* or there...
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*/
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/*
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* Partition info commands
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*
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* I do not know what those are for at this point
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*/
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#define SMU_CMD_PARTITION_COMMAND 0x3e
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/*
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* Fan control
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*
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* This is a "mux" for fan control commands, first byte is the
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* "sub" command.
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*/
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#define SMU_CMD_FAN_COMMAND 0x4a
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/*
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* Battery access
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*
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* Same command number as the PMU, could it be same syntax ?
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*/
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#define SMU_CMD_BATTERY_COMMAND 0x6f
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#define SMU_CMD_GET_BATTERY_INFO 0x00
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/*
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* Real time clock control
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*
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* This is a "mux", first data byte contains the "sub" command.
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* The "RTC" part of the SMU controls the date, time, powerup
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* timer, but also a PRAM
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*
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* Dates are in BCD format on 7 bytes:
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* [sec] [min] [hour] [weekday] [month day] [month] [year]
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* with month being 1 based and year minus 100
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*/
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#define SMU_CMD_RTC_COMMAND 0x8e
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#define SMU_CMD_RTC_SET_PWRUP_TIMER 0x00 /* i: 7 bytes date */
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#define SMU_CMD_RTC_GET_PWRUP_TIMER 0x01 /* o: 7 bytes date */
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#define SMU_CMD_RTC_STOP_PWRUP_TIMER 0x02
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#define SMU_CMD_RTC_SET_PRAM_BYTE_ACC 0x20 /* i: 1 byte (address?) */
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#define SMU_CMD_RTC_SET_PRAM_AUTOINC 0x21 /* i: 1 byte (data?) */
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#define SMU_CMD_RTC_SET_PRAM_LO_BYTES 0x22 /* i: 10 bytes */
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#define SMU_CMD_RTC_SET_PRAM_HI_BYTES 0x23 /* i: 10 bytes */
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#define SMU_CMD_RTC_GET_PRAM_BYTE 0x28 /* i: 1 bytes (address?) */
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#define SMU_CMD_RTC_GET_PRAM_LO_BYTES 0x29 /* o: 10 bytes */
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#define SMU_CMD_RTC_GET_PRAM_HI_BYTES 0x2a /* o: 10 bytes */
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#define SMU_CMD_RTC_SET_DATETIME 0x80 /* i: 7 bytes date */
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#define SMU_CMD_RTC_GET_DATETIME 0x81 /* o: 7 bytes date */
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/*
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* i2c commands
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*
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* To issue an i2c command, first is to send a parameter block to the
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* the SMU. This is a command of type 0x9a with 9 bytes of header
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* eventually followed by data for a write:
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*
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* 0: bus number (from device-tree usually, SMU has lots of busses !)
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* 1: transfer type/format (see below)
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* 2: device address. For combined and combined4 type transfers, this
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* is the "write" version of the address (bit 0x01 cleared)
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* 3: subaddress length (0..3)
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* 4: subaddress byte 0 (or only byte for subaddress length 1)
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* 5: subaddress byte 1
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* 6: subaddress byte 2
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* 7: combined address (device address for combined mode data phase)
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* 8: data length
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*
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* The transfer types are the same good old Apple ones it seems,
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* that is:
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* - 0x00: Simple transfer
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* - 0x01: Subaddress transfer (addr write + data tx, no restart)
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* - 0x02: Combined transfer (addr write + restart + data tx)
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*
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* This is then followed by actual data for a write.
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*
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* At this point, the OF driver seems to have a limitation on transfer
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* sizes of 0xd bytes on reads and 0x5 bytes on writes. I do not know
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* wether this is just an OF limit due to some temporary buffer size
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* or if this is an SMU imposed limit. This driver has the same limitation
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* for now as I use a 0x10 bytes temporary buffer as well
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*
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* Once that is completed, a response is expected from the SMU. This is
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* obtained via a command of type 0x9a with a length of 1 byte containing
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* 0 as the data byte. OF also fills the rest of the data buffer with 0xff's
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* though I can't tell yet if this is actually necessary. Once this command
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* is complete, at this point, all I can tell is what OF does. OF tests
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* byte 0 of the reply:
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* - on read, 0xfe or 0xfc : bus is busy, wait (see below) or nak ?
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* - on read, 0x00 or 0x01 : reply is in buffer (after the byte 0)
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* - on write, < 0 -> failure (immediate exit)
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* - else, OF just exists (without error, weird)
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*
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* So on read, there is this wait-for-busy thing when getting a 0xfc or
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* 0xfe result. OF does a loop of up to 64 retries, waiting 20ms and
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* doing the above again until either the retries expire or the result
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* is no longer 0xfe or 0xfc
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*
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* The Darwin I2C driver is less subtle though. On any non-success status
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* from the response command, it waits 5ms and tries again up to 20 times,
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* it doesn't differenciate between fatal errors or "busy" status.
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*
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* This driver provides an asynchronous paramblock based i2c command
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* interface to be used either directly by low level code or by a higher
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* level driver interfacing to the linux i2c layer. The current
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* implementation of this relies on working timers & timer interrupts
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* though, so be careful of calling context for now. This may be "fixed"
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* in the future by adding a polling facility.
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*/
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#define SMU_CMD_I2C_COMMAND 0x9a
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/* transfer types */
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#define SMU_I2C_TRANSFER_SIMPLE 0x00
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#define SMU_I2C_TRANSFER_STDSUB 0x01
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#define SMU_I2C_TRANSFER_COMBINED 0x02
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/*
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* Power supply control
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*
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* The "sub" command is an ASCII string in the data, the
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* data lenght is that of the string.
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*
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* The VSLEW command can be used to get or set the voltage slewing.
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* - lenght 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
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* reply at data offset 6, 7 and 8.
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* - lenght 8 ("VSLEWxyz") has 3 additional bytes appended, and is
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* used to set the voltage slewing point. The SMU replies with "DONE"
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* I yet have to figure out their exact meaning of those 3 bytes in
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* both cases.
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*
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*/
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#define SMU_CMD_POWER_COMMAND 0xaa
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#define SMU_CMD_POWER_RESTART "RESTART"
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#define SMU_CMD_POWER_SHUTDOWN "SHUTDOWN"
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#define SMU_CMD_POWER_VOLTAGE_SLEW "VSLEW"
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/* Misc commands
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*
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* This command seem to be a grab bag of various things
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*/
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#define SMU_CMD_MISC_df_COMMAND 0xdf
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#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02 /* i: 1 byte */
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#define SMU_CMD_MISC_df_NMI_OPTION 0x04
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/*
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* Version info commands
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*
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* I haven't quite tried to figure out how these work
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*/
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#define SMU_CMD_VERSION_COMMAND 0xea
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/*
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* Misc commands
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*
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* This command seem to be a grab bag of various things
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*/
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#define SMU_CMD_MISC_ee_COMMAND 0xee
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#define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02
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#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */
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#define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */
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/*
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* - Kernel side interface -
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*/
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#ifdef __KERNEL__
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/*
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* Asynchronous SMU commands
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*
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* Fill up this structure and submit it via smu_queue_command(),
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* and get notified by the optional done() callback, or because
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* status becomes != 1
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*/
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struct smu_cmd;
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struct smu_cmd
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{
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/* public */
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u8 cmd; /* command */
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int data_len; /* data len */
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int reply_len; /* reply len */
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void *data_buf; /* data buffer */
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void *reply_buf; /* reply buffer */
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int status; /* command status */
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void (*done)(struct smu_cmd *cmd, void *misc);
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void *misc;
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/* private */
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struct list_head link;
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};
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/*
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* Queues an SMU command, all fields have to be initialized
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*/
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extern int smu_queue_cmd(struct smu_cmd *cmd);
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/*
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* Simple command wrapper. This structure embeds a small buffer
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* to ease sending simple SMU commands from the stack
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*/
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struct smu_simple_cmd
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{
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struct smu_cmd cmd;
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u8 buffer[16];
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};
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/*
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* Queues a simple command. All fields will be initialized by that
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* function
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*/
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extern int smu_queue_simple(struct smu_simple_cmd *scmd, u8 command,
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unsigned int data_len,
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void (*done)(struct smu_cmd *cmd, void *misc),
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void *misc,
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...);
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/*
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* Completion helper. Pass it to smu_queue_simple or as 'done'
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* member to smu_queue_cmd, it will call complete() on the struct
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* completion passed in the "misc" argument
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*/
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extern void smu_done_complete(struct smu_cmd *cmd, void *misc);
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/*
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* Synchronous helpers. Will spin-wait for completion of a command
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*/
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extern void smu_spinwait_cmd(struct smu_cmd *cmd);
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static inline void smu_spinwait_simple(struct smu_simple_cmd *scmd)
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{
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smu_spinwait_cmd(&scmd->cmd);
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}
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/*
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* Poll routine to call if blocked with irqs off
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*/
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extern void smu_poll(void);
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/*
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* Init routine, presence check....
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*/
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extern int smu_init(void);
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extern int smu_present(void);
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struct of_device;
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extern struct of_device *smu_get_ofdev(void);
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/*
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* Common command wrappers
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*/
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extern void smu_shutdown(void);
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extern void smu_restart(void);
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struct rtc_time;
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extern int smu_get_rtc_time(struct rtc_time *time, int spinwait);
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extern int smu_set_rtc_time(struct rtc_time *time, int spinwait);
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/*
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* SMU command buffer absolute address, exported by pmac_setup,
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* this is allocated very early during boot.
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*/
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extern unsigned long smu_cmdbuf_abs;
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/*
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* Kenrel asynchronous i2c interface
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*/
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/* SMU i2c header, exactly matches i2c header on wire */
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struct smu_i2c_param
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{
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u8 bus; /* SMU bus ID (from device tree) */
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u8 type; /* i2c transfer type */
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u8 devaddr; /* device address (includes direction) */
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u8 sublen; /* subaddress length */
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u8 subaddr[3]; /* subaddress */
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u8 caddr; /* combined address, filled by SMU driver */
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u8 datalen; /* length of transfer */
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u8 data[7]; /* data */
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};
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#define SMU_I2C_READ_MAX 0x0d
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#define SMU_I2C_WRITE_MAX 0x05
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struct smu_i2c_cmd
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{
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/* public */
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struct smu_i2c_param info;
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void (*done)(struct smu_i2c_cmd *cmd, void *misc);
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void *misc;
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int status; /* 1 = pending, 0 = ok, <0 = fail */
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/* private */
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struct smu_cmd scmd;
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int read;
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int stage;
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int retries;
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u8 pdata[0x10];
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struct list_head link;
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};
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/*
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* Call this to queue an i2c command to the SMU. You must fill info,
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* including info.data for a write, done and misc.
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* For now, no polling interface is provided so you have to use completion
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* callback.
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*/
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extern int smu_queue_i2c(struct smu_i2c_cmd *cmd);
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#endif /* __KERNEL__ */
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/*
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* - Userland interface -
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*/
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/*
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* A given instance of the device can be configured for 2 different
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* things at the moment:
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*
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* - sending SMU commands (default at open() time)
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* - receiving SMU events (not yet implemented)
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*
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* Commands are written with write() of a command block. They can be
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* "driver" commands (for example to switch to event reception mode)
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* or real SMU commands. They are made of a header followed by command
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* data if any.
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*
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* For SMU commands (not for driver commands), you can then read() back
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* a reply. The reader will be blocked or not depending on how the device
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* file is opened. poll() isn't implemented yet. The reply will consist
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* of a header as well, followed by the reply data if any. You should
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* always provide a buffer large enough for the maximum reply data, I
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* recommand one page.
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*
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* It is illegal to send SMU commands through a file descriptor configured
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* for events reception
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*
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*/
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struct smu_user_cmd_hdr
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{
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__u32 cmdtype;
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#define SMU_CMDTYPE_SMU 0 /* SMU command */
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#define SMU_CMDTYPE_WANTS_EVENTS 1 /* switch fd to events mode */
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__u8 cmd; /* SMU command byte */
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__u32 data_len; /* Lenght of data following */
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};
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struct smu_user_reply_hdr
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{
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__u32 status; /* Command status */
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__u32 reply_len; /* Lenght of data follwing */
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};
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#endif /* _SMU_H */
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