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#ifndef _ASM_M32R_CACHE_H
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#define _ASM_M32R_CACHE_H
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/* $Id$ */
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/* L1 cache line size */
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#define L1_CACHE_SHIFT 4
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define L1_CACHE_SHIFT_MAX 4
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#endif /* _ASM_M32R_CACHE_H */
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