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184 lines
5.1 KiB
184 lines
5.1 KiB
/*
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* include/asm-xtensa/page.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version2 as
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* published by the Free Software Foundation.
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*
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* Copyright (C) 2001 - 2007 Tensilica Inc.
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*/
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#ifndef _XTENSA_PAGE_H
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#define _XTENSA_PAGE_H
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#include <asm/processor.h>
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#include <asm/types.h>
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#include <asm/cache.h>
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#include <platform/hardware.h>
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/*
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* Fixed TLB translations in the processor.
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*/
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#define XCHAL_KSEG_CACHED_VADDR 0xd0000000
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#define XCHAL_KSEG_BYPASS_VADDR 0xd8000000
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#define XCHAL_KSEG_PADDR 0x00000000
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#define XCHAL_KSEG_SIZE 0x08000000
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/*
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* PAGE_SHIFT determines the page size
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*/
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (__XTENSA_UL_CONST(1) << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE-1))
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#ifdef CONFIG_MMU
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#define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR
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#define MAX_MEM_PFN XCHAL_KSEG_SIZE
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#else
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#define PAGE_OFFSET 0
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#define MAX_MEM_PFN (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE)
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#endif
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#define PGTABLE_START 0x80000000
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/*
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* Cache aliasing:
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*
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* If the cache size for one way is greater than the page size, we have to
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* deal with cache aliasing. The cache index is wider than the page size:
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*
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* | |cache| cache index
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* | pfn |off| virtual address
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* |xxxx:X|zzz|
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* | : | |
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* | \ / | |
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* |trans.| |
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* | / \ | |
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* |yyyy:Y|zzz| physical address
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*
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* When the page number is translated to the physical page address, the lowest
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* bit(s) (X) that are part of the cache index are also translated (Y).
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* If this translation changes bit(s) (X), the cache index is also afected,
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* thus resulting in a different cache line than before.
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* The kernel does not provide a mechanism to ensure that the page color
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* (represented by this bit) remains the same when allocated or when pages
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* are remapped. When user pages are mapped into kernel space, the color of
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* the page might also change.
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*
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* We use the address space VMALLOC_END ... VMALLOC_END + DCACHE_WAY_SIZE * 2
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* to temporarily map a patch so we can match the color.
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*/
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#if DCACHE_WAY_SIZE > PAGE_SIZE
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# define DCACHE_ALIAS_ORDER (DCACHE_WAY_SHIFT - PAGE_SHIFT)
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# define DCACHE_ALIAS_MASK (PAGE_MASK & (DCACHE_WAY_SIZE - 1))
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# define DCACHE_ALIAS(a) (((a) & DCACHE_ALIAS_MASK) >> PAGE_SHIFT)
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# define DCACHE_ALIAS_EQ(a,b) ((((a) ^ (b)) & DCACHE_ALIAS_MASK) == 0)
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#else
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# define DCACHE_ALIAS_ORDER 0
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#endif
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#if ICACHE_WAY_SIZE > PAGE_SIZE
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# define ICACHE_ALIAS_ORDER (ICACHE_WAY_SHIFT - PAGE_SHIFT)
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# define ICACHE_ALIAS_MASK (PAGE_MASK & (ICACHE_WAY_SIZE - 1))
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# define ICACHE_ALIAS(a) (((a) & ICACHE_ALIAS_MASK) >> PAGE_SHIFT)
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# define ICACHE_ALIAS_EQ(a,b) ((((a) ^ (b)) & ICACHE_ALIAS_MASK) == 0)
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#else
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# define ICACHE_ALIAS_ORDER 0
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#endif
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#ifdef __ASSEMBLY__
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#define __pgprot(x) (x)
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#else
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/*
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* These are used to make use of C type-checking..
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*/
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typedef struct { unsigned long pte; } pte_t; /* page table entry */
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typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */
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typedef struct { unsigned long pgprot; } pgprot_t;
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typedef struct page *pgtable_t;
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#define pte_val(x) ((x).pte)
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#define pgd_val(x) ((x).pgd)
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#define pgprot_val(x) ((x).pgprot)
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#define __pte(x) ((pte_t) { (x) } )
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#define __pgd(x) ((pgd_t) { (x) } )
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#define __pgprot(x) ((pgprot_t) { (x) } )
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/*
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* Pure 2^n version of get_order
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* Use 'nsau' instructions if supported by the processor or the generic version.
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*/
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#if XCHAL_HAVE_NSA
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static inline __attribute_const__ int get_order(unsigned long size)
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{
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int lz;
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asm ("nsau %0, %1" : "=r" (lz) : "r" ((size - 1) >> PAGE_SHIFT));
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return 32 - lz;
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}
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#else
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# include <asm-generic/getorder.h>
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#endif
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struct page;
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extern void clear_page(void *page);
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extern void copy_page(void *to, void *from);
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/*
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* If we have cache aliasing and writeback caches, we might have to do
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* some extra work
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*/
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#if DCACHE_WAY_SIZE > PAGE_SIZE
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extern void clear_user_page(void*, unsigned long, struct page*);
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extern void copy_user_page(void*, void*, unsigned long, struct page*);
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#else
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# define clear_user_page(page, vaddr, pg) clear_page(page)
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# define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
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#endif
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/*
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* This handles the memory map. We handle pages at
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* XCHAL_KSEG_CACHED_VADDR for kernels with 32 bit address space.
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* These macros are for conversion of kernel address, not user
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* addresses.
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*/
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#define ARCH_PFN_OFFSET (PLATFORM_DEFAULT_MEM_START >> PAGE_SHIFT)
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#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
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#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
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#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && ((pfn) - ARCH_PFN_OFFSET) < max_mapnr)
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#ifdef CONFIG_DISCONTIGMEM
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# error CONFIG_DISCONTIGMEM not supported
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#endif
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#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
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#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT)
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#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
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#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
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#ifdef CONFIG_MMU
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#define WANT_PAGE_VIRTUAL
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#endif
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#endif /* __ASSEMBLY__ */
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#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#include <asm-generic/memory_model.h>
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#endif /* _XTENSA_PAGE_H */
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