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971 lines
25 KiB
971 lines
25 KiB
/*
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* arch/arm/mach-kirkwood/common.c
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*
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* Core functions for Marvell Kirkwood SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/mbus.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/mv643xx_i2c.h>
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#include <linux/ata_platform.h>
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#include <linux/mtd/nand.h>
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#include <linux/spi/orion_spi.h>
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#include <net/dsa.h>
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#include <asm/page.h>
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#include <asm/timex.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/kirkwood.h>
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#include <mach/bridge-regs.h>
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#include <plat/cache-feroceon-l2.h>
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#include <plat/ehci-orion.h>
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#include <plat/mvsdio.h>
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#include <plat/mv_xor.h>
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#include <plat/orion_nand.h>
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#include <plat/orion_wdt.h>
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#include <plat/time.h>
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#include "common.h"
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc kirkwood_io_desc[] __initdata = {
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{
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.virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
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.length = KIRKWOOD_PCIE_IO_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = KIRKWOOD_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
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.length = KIRKWOOD_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init kirkwood_map_io(void)
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{
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iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
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}
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/*
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* Default clock control bits. Any bit _not_ set in this variable
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* will be cleared from the hardware after platform devices have been
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* registered. Some reserved bits must be set to 1.
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*/
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unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
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/*****************************************************************************
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* EHCI
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****************************************************************************/
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static struct orion_ehci_data kirkwood_ehci_data = {
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.dram = &kirkwood_mbus_dram_info,
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.phy_version = EHCI_PHY_NA,
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};
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static u64 ehci_dmamask = 0xffffffffUL;
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/*****************************************************************************
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* EHCI0
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****************************************************************************/
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static struct resource kirkwood_ehci_resources[] = {
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{
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.start = USB_PHYS_BASE,
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.end = USB_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_KIRKWOOD_USB,
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.end = IRQ_KIRKWOOD_USB,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_ehci = {
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.name = "orion-ehci",
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.id = 0,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &kirkwood_ehci_data,
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},
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.resource = kirkwood_ehci_resources,
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.num_resources = ARRAY_SIZE(kirkwood_ehci_resources),
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};
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void __init kirkwood_ehci_init(void)
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{
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kirkwood_clk_ctrl |= CGC_USB0;
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platform_device_register(&kirkwood_ehci);
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}
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/*****************************************************************************
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* GE00
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****************************************************************************/
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struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
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.dram = &kirkwood_mbus_dram_info,
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};
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static struct resource kirkwood_ge00_shared_resources[] = {
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{
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.name = "ge00 base",
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.start = GE00_PHYS_BASE + 0x2000,
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.end = GE00_PHYS_BASE + 0x3fff,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "ge00 err irq",
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.start = IRQ_KIRKWOOD_GE00_ERR,
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.end = IRQ_KIRKWOOD_GE00_ERR,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_ge00_shared = {
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.name = MV643XX_ETH_SHARED_NAME,
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.id = 0,
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.dev = {
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.platform_data = &kirkwood_ge00_shared_data,
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},
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.num_resources = ARRAY_SIZE(kirkwood_ge00_shared_resources),
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.resource = kirkwood_ge00_shared_resources,
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};
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static struct resource kirkwood_ge00_resources[] = {
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{
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.name = "ge00 irq",
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.start = IRQ_KIRKWOOD_GE00_SUM,
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.end = IRQ_KIRKWOOD_GE00_SUM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_ge00 = {
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.name = MV643XX_ETH_NAME,
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.id = 0,
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.num_resources = 1,
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.resource = kirkwood_ge00_resources,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
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{
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kirkwood_clk_ctrl |= CGC_GE0;
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eth_data->shared = &kirkwood_ge00_shared;
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kirkwood_ge00.dev.platform_data = eth_data;
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platform_device_register(&kirkwood_ge00_shared);
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platform_device_register(&kirkwood_ge00);
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}
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/*****************************************************************************
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* GE01
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****************************************************************************/
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struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = {
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.dram = &kirkwood_mbus_dram_info,
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.shared_smi = &kirkwood_ge00_shared,
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};
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static struct resource kirkwood_ge01_shared_resources[] = {
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{
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.name = "ge01 base",
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.start = GE01_PHYS_BASE + 0x2000,
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.end = GE01_PHYS_BASE + 0x3fff,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "ge01 err irq",
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.start = IRQ_KIRKWOOD_GE01_ERR,
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.end = IRQ_KIRKWOOD_GE01_ERR,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_ge01_shared = {
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.name = MV643XX_ETH_SHARED_NAME,
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.id = 1,
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.dev = {
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.platform_data = &kirkwood_ge01_shared_data,
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},
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.num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources),
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.resource = kirkwood_ge01_shared_resources,
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};
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static struct resource kirkwood_ge01_resources[] = {
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{
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.name = "ge01 irq",
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.start = IRQ_KIRKWOOD_GE01_SUM,
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.end = IRQ_KIRKWOOD_GE01_SUM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_ge01 = {
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.name = MV643XX_ETH_NAME,
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.id = 1,
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.num_resources = 1,
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.resource = kirkwood_ge01_resources,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
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{
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kirkwood_clk_ctrl |= CGC_GE1;
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eth_data->shared = &kirkwood_ge01_shared;
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kirkwood_ge01.dev.platform_data = eth_data;
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platform_device_register(&kirkwood_ge01_shared);
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platform_device_register(&kirkwood_ge01);
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}
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/*****************************************************************************
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* Ethernet switch
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****************************************************************************/
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static struct resource kirkwood_switch_resources[] = {
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{
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_switch_device = {
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.name = "dsa",
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.id = 0,
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.num_resources = 0,
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.resource = kirkwood_switch_resources,
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};
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void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
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{
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int i;
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if (irq != NO_IRQ) {
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kirkwood_switch_resources[0].start = irq;
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kirkwood_switch_resources[0].end = irq;
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kirkwood_switch_device.num_resources = 1;
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}
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d->netdev = &kirkwood_ge00.dev;
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for (i = 0; i < d->nr_chips; i++)
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d->chip[i].mii_bus = &kirkwood_ge00_shared.dev;
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kirkwood_switch_device.dev.platform_data = d;
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platform_device_register(&kirkwood_switch_device);
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}
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/*****************************************************************************
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* NAND flash
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****************************************************************************/
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static struct resource kirkwood_nand_resource = {
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.flags = IORESOURCE_MEM,
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.start = KIRKWOOD_NAND_MEM_PHYS_BASE,
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.end = KIRKWOOD_NAND_MEM_PHYS_BASE +
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KIRKWOOD_NAND_MEM_SIZE - 1,
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};
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static struct orion_nand_data kirkwood_nand_data = {
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.cle = 0,
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.ale = 1,
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.width = 8,
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};
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static struct platform_device kirkwood_nand_flash = {
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.name = "orion_nand",
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.id = -1,
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.dev = {
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.platform_data = &kirkwood_nand_data,
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},
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.resource = &kirkwood_nand_resource,
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.num_resources = 1,
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};
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void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
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int chip_delay)
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{
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kirkwood_clk_ctrl |= CGC_RUNIT;
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kirkwood_nand_data.parts = parts;
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kirkwood_nand_data.nr_parts = nr_parts;
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kirkwood_nand_data.chip_delay = chip_delay;
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platform_device_register(&kirkwood_nand_flash);
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}
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/*****************************************************************************
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* SoC RTC
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****************************************************************************/
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static struct resource kirkwood_rtc_resource = {
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.start = RTC_PHYS_BASE,
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.end = RTC_PHYS_BASE + SZ_16 - 1,
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.flags = IORESOURCE_MEM,
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};
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static void __init kirkwood_rtc_init(void)
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{
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platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
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}
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/*****************************************************************************
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* SATA
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****************************************************************************/
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static struct resource kirkwood_sata_resources[] = {
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{
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.name = "sata base",
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.start = SATA_PHYS_BASE,
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.end = SATA_PHYS_BASE + 0x5000 - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "sata irq",
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.start = IRQ_KIRKWOOD_SATA,
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.end = IRQ_KIRKWOOD_SATA,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_sata = {
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.name = "sata_mv",
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.id = 0,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(kirkwood_sata_resources),
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.resource = kirkwood_sata_resources,
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};
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void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
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{
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kirkwood_clk_ctrl |= CGC_SATA0;
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if (sata_data->n_ports > 1)
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kirkwood_clk_ctrl |= CGC_SATA1;
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sata_data->dram = &kirkwood_mbus_dram_info;
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kirkwood_sata.dev.platform_data = sata_data;
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platform_device_register(&kirkwood_sata);
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}
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/*****************************************************************************
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* SD/SDIO/MMC
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****************************************************************************/
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static struct resource mvsdio_resources[] = {
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[0] = {
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.start = SDIO_PHYS_BASE,
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.end = SDIO_PHYS_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_KIRKWOOD_SDIO,
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.end = IRQ_KIRKWOOD_SDIO,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 mvsdio_dmamask = 0xffffffffUL;
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static struct platform_device kirkwood_sdio = {
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.name = "mvsdio",
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.id = -1,
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.dev = {
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.dma_mask = &mvsdio_dmamask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(mvsdio_resources),
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.resource = mvsdio_resources,
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};
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void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
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{
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u32 dev, rev;
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kirkwood_pcie_id(&dev, &rev);
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if (rev == 0) /* catch all Kirkwood Z0's */
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mvsdio_data->clock = 100000000;
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else
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mvsdio_data->clock = 200000000;
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mvsdio_data->dram = &kirkwood_mbus_dram_info;
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kirkwood_clk_ctrl |= CGC_SDIO;
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kirkwood_sdio.dev.platform_data = mvsdio_data;
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platform_device_register(&kirkwood_sdio);
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}
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/*****************************************************************************
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* SPI
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****************************************************************************/
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static struct orion_spi_info kirkwood_spi_plat_data = {
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};
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static struct resource kirkwood_spi_resources[] = {
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{
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.start = SPI_PHYS_BASE,
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.end = SPI_PHYS_BASE + SZ_512 - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device kirkwood_spi = {
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.name = "orion_spi",
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.id = 0,
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.resource = kirkwood_spi_resources,
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.dev = {
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.platform_data = &kirkwood_spi_plat_data,
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},
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.num_resources = ARRAY_SIZE(kirkwood_spi_resources),
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};
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void __init kirkwood_spi_init()
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{
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kirkwood_clk_ctrl |= CGC_RUNIT;
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platform_device_register(&kirkwood_spi);
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}
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/*****************************************************************************
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* I2C
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****************************************************************************/
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static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
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.freq_m = 8, /* assumes 166 MHz TCLK */
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.freq_n = 3,
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.timeout = 1000, /* Default timeout of 1 second */
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};
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static struct resource kirkwood_i2c_resources[] = {
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{
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.start = I2C_PHYS_BASE,
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.end = I2C_PHYS_BASE + 0x1f,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_KIRKWOOD_TWSI,
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.end = IRQ_KIRKWOOD_TWSI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_i2c = {
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.name = MV64XXX_I2C_CTLR_NAME,
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.id = 0,
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.num_resources = ARRAY_SIZE(kirkwood_i2c_resources),
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.resource = kirkwood_i2c_resources,
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.dev = {
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.platform_data = &kirkwood_i2c_pdata,
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},
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};
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void __init kirkwood_i2c_init(void)
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{
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platform_device_register(&kirkwood_i2c);
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}
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|
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/*****************************************************************************
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* UART0
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****************************************************************************/
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static struct plat_serial8250_port kirkwood_uart0_data[] = {
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{
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.mapbase = UART0_PHYS_BASE,
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.membase = (char *)UART0_VIRT_BASE,
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.irq = IRQ_KIRKWOOD_UART_0,
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.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = 0,
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}, {
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},
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};
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|
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static struct resource kirkwood_uart0_resources[] = {
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{
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.start = UART0_PHYS_BASE,
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.end = UART0_PHYS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_KIRKWOOD_UART_0,
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.end = IRQ_KIRKWOOD_UART_0,
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.flags = IORESOURCE_IRQ,
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},
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};
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|
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static struct platform_device kirkwood_uart0 = {
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.name = "serial8250",
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.id = 0,
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.dev = {
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.platform_data = kirkwood_uart0_data,
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},
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.resource = kirkwood_uart0_resources,
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.num_resources = ARRAY_SIZE(kirkwood_uart0_resources),
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};
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|
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void __init kirkwood_uart0_init(void)
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|
{
|
|
platform_device_register(&kirkwood_uart0);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* UART1
|
|
****************************************************************************/
|
|
static struct plat_serial8250_port kirkwood_uart1_data[] = {
|
|
{
|
|
.mapbase = UART1_PHYS_BASE,
|
|
.membase = (char *)UART1_VIRT_BASE,
|
|
.irq = IRQ_KIRKWOOD_UART_1,
|
|
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
.uartclk = 0,
|
|
}, {
|
|
},
|
|
};
|
|
|
|
static struct resource kirkwood_uart1_resources[] = {
|
|
{
|
|
.start = UART1_PHYS_BASE,
|
|
.end = UART1_PHYS_BASE + 0xff,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.start = IRQ_KIRKWOOD_UART_1,
|
|
.end = IRQ_KIRKWOOD_UART_1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device kirkwood_uart1 = {
|
|
.name = "serial8250",
|
|
.id = 1,
|
|
.dev = {
|
|
.platform_data = kirkwood_uart1_data,
|
|
},
|
|
.resource = kirkwood_uart1_resources,
|
|
.num_resources = ARRAY_SIZE(kirkwood_uart1_resources),
|
|
};
|
|
|
|
void __init kirkwood_uart1_init(void)
|
|
{
|
|
platform_device_register(&kirkwood_uart1);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* Cryptographic Engines and Security Accelerator (CESA)
|
|
****************************************************************************/
|
|
|
|
static struct resource kirkwood_crypto_res[] = {
|
|
{
|
|
.name = "regs",
|
|
.start = CRYPTO_PHYS_BASE,
|
|
.end = CRYPTO_PHYS_BASE + 0xffff,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.name = "sram",
|
|
.start = KIRKWOOD_SRAM_PHYS_BASE,
|
|
.end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.name = "crypto interrupt",
|
|
.start = IRQ_KIRKWOOD_CRYPTO,
|
|
.end = IRQ_KIRKWOOD_CRYPTO,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device kirkwood_crypto_device = {
|
|
.name = "mv_crypto",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(kirkwood_crypto_res),
|
|
.resource = kirkwood_crypto_res,
|
|
};
|
|
|
|
void __init kirkwood_crypto_init(void)
|
|
{
|
|
kirkwood_clk_ctrl |= CGC_CRYPTO;
|
|
platform_device_register(&kirkwood_crypto_device);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* XOR
|
|
****************************************************************************/
|
|
static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
|
|
.dram = &kirkwood_mbus_dram_info,
|
|
};
|
|
|
|
static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
|
|
|
|
|
|
/*****************************************************************************
|
|
* XOR0
|
|
****************************************************************************/
|
|
static struct resource kirkwood_xor0_shared_resources[] = {
|
|
{
|
|
.name = "xor 0 low",
|
|
.start = XOR0_PHYS_BASE,
|
|
.end = XOR0_PHYS_BASE + 0xff,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.name = "xor 0 high",
|
|
.start = XOR0_HIGH_PHYS_BASE,
|
|
.end = XOR0_HIGH_PHYS_BASE + 0xff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device kirkwood_xor0_shared = {
|
|
.name = MV_XOR_SHARED_NAME,
|
|
.id = 0,
|
|
.dev = {
|
|
.platform_data = &kirkwood_xor_shared_data,
|
|
},
|
|
.num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources),
|
|
.resource = kirkwood_xor0_shared_resources,
|
|
};
|
|
|
|
static struct resource kirkwood_xor00_resources[] = {
|
|
[0] = {
|
|
.start = IRQ_KIRKWOOD_XOR_00,
|
|
.end = IRQ_KIRKWOOD_XOR_00,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct mv_xor_platform_data kirkwood_xor00_data = {
|
|
.shared = &kirkwood_xor0_shared,
|
|
.hw_id = 0,
|
|
.pool_size = PAGE_SIZE,
|
|
};
|
|
|
|
static struct platform_device kirkwood_xor00_channel = {
|
|
.name = MV_XOR_NAME,
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(kirkwood_xor00_resources),
|
|
.resource = kirkwood_xor00_resources,
|
|
.dev = {
|
|
.dma_mask = &kirkwood_xor_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(64),
|
|
.platform_data = (void *)&kirkwood_xor00_data,
|
|
},
|
|
};
|
|
|
|
static struct resource kirkwood_xor01_resources[] = {
|
|
[0] = {
|
|
.start = IRQ_KIRKWOOD_XOR_01,
|
|
.end = IRQ_KIRKWOOD_XOR_01,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct mv_xor_platform_data kirkwood_xor01_data = {
|
|
.shared = &kirkwood_xor0_shared,
|
|
.hw_id = 1,
|
|
.pool_size = PAGE_SIZE,
|
|
};
|
|
|
|
static struct platform_device kirkwood_xor01_channel = {
|
|
.name = MV_XOR_NAME,
|
|
.id = 1,
|
|
.num_resources = ARRAY_SIZE(kirkwood_xor01_resources),
|
|
.resource = kirkwood_xor01_resources,
|
|
.dev = {
|
|
.dma_mask = &kirkwood_xor_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(64),
|
|
.platform_data = (void *)&kirkwood_xor01_data,
|
|
},
|
|
};
|
|
|
|
static void __init kirkwood_xor0_init(void)
|
|
{
|
|
kirkwood_clk_ctrl |= CGC_XOR0;
|
|
platform_device_register(&kirkwood_xor0_shared);
|
|
|
|
/*
|
|
* two engines can't do memset simultaneously, this limitation
|
|
* satisfied by removing memset support from one of the engines.
|
|
*/
|
|
dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
|
|
dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
|
|
platform_device_register(&kirkwood_xor00_channel);
|
|
|
|
dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
|
|
dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
|
|
dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
|
|
platform_device_register(&kirkwood_xor01_channel);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* XOR1
|
|
****************************************************************************/
|
|
static struct resource kirkwood_xor1_shared_resources[] = {
|
|
{
|
|
.name = "xor 1 low",
|
|
.start = XOR1_PHYS_BASE,
|
|
.end = XOR1_PHYS_BASE + 0xff,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.name = "xor 1 high",
|
|
.start = XOR1_HIGH_PHYS_BASE,
|
|
.end = XOR1_HIGH_PHYS_BASE + 0xff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device kirkwood_xor1_shared = {
|
|
.name = MV_XOR_SHARED_NAME,
|
|
.id = 1,
|
|
.dev = {
|
|
.platform_data = &kirkwood_xor_shared_data,
|
|
},
|
|
.num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources),
|
|
.resource = kirkwood_xor1_shared_resources,
|
|
};
|
|
|
|
static struct resource kirkwood_xor10_resources[] = {
|
|
[0] = {
|
|
.start = IRQ_KIRKWOOD_XOR_10,
|
|
.end = IRQ_KIRKWOOD_XOR_10,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct mv_xor_platform_data kirkwood_xor10_data = {
|
|
.shared = &kirkwood_xor1_shared,
|
|
.hw_id = 0,
|
|
.pool_size = PAGE_SIZE,
|
|
};
|
|
|
|
static struct platform_device kirkwood_xor10_channel = {
|
|
.name = MV_XOR_NAME,
|
|
.id = 2,
|
|
.num_resources = ARRAY_SIZE(kirkwood_xor10_resources),
|
|
.resource = kirkwood_xor10_resources,
|
|
.dev = {
|
|
.dma_mask = &kirkwood_xor_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(64),
|
|
.platform_data = (void *)&kirkwood_xor10_data,
|
|
},
|
|
};
|
|
|
|
static struct resource kirkwood_xor11_resources[] = {
|
|
[0] = {
|
|
.start = IRQ_KIRKWOOD_XOR_11,
|
|
.end = IRQ_KIRKWOOD_XOR_11,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct mv_xor_platform_data kirkwood_xor11_data = {
|
|
.shared = &kirkwood_xor1_shared,
|
|
.hw_id = 1,
|
|
.pool_size = PAGE_SIZE,
|
|
};
|
|
|
|
static struct platform_device kirkwood_xor11_channel = {
|
|
.name = MV_XOR_NAME,
|
|
.id = 3,
|
|
.num_resources = ARRAY_SIZE(kirkwood_xor11_resources),
|
|
.resource = kirkwood_xor11_resources,
|
|
.dev = {
|
|
.dma_mask = &kirkwood_xor_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(64),
|
|
.platform_data = (void *)&kirkwood_xor11_data,
|
|
},
|
|
};
|
|
|
|
static void __init kirkwood_xor1_init(void)
|
|
{
|
|
kirkwood_clk_ctrl |= CGC_XOR1;
|
|
platform_device_register(&kirkwood_xor1_shared);
|
|
|
|
/*
|
|
* two engines can't do memset simultaneously, this limitation
|
|
* satisfied by removing memset support from one of the engines.
|
|
*/
|
|
dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
|
|
dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
|
|
platform_device_register(&kirkwood_xor10_channel);
|
|
|
|
dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
|
|
dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
|
|
dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
|
|
platform_device_register(&kirkwood_xor11_channel);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* Watchdog
|
|
****************************************************************************/
|
|
static struct orion_wdt_platform_data kirkwood_wdt_data = {
|
|
.tclk = 0,
|
|
};
|
|
|
|
static struct platform_device kirkwood_wdt_device = {
|
|
.name = "orion_wdt",
|
|
.id = -1,
|
|
.dev = {
|
|
.platform_data = &kirkwood_wdt_data,
|
|
},
|
|
.num_resources = 0,
|
|
};
|
|
|
|
static void __init kirkwood_wdt_init(void)
|
|
{
|
|
kirkwood_wdt_data.tclk = kirkwood_tclk;
|
|
platform_device_register(&kirkwood_wdt_device);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* Time handling
|
|
****************************************************************************/
|
|
int kirkwood_tclk;
|
|
|
|
int __init kirkwood_find_tclk(void)
|
|
{
|
|
u32 dev, rev;
|
|
|
|
kirkwood_pcie_id(&dev, &rev);
|
|
if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
|
|
rev == MV88F6281_REV_A1))
|
|
return 200000000;
|
|
|
|
return 166666667;
|
|
}
|
|
|
|
static void kirkwood_timer_init(void)
|
|
{
|
|
kirkwood_tclk = kirkwood_find_tclk();
|
|
orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
|
|
}
|
|
|
|
struct sys_timer kirkwood_timer = {
|
|
.init = kirkwood_timer_init,
|
|
};
|
|
|
|
|
|
/*****************************************************************************
|
|
* General
|
|
****************************************************************************/
|
|
/*
|
|
* Identify device ID and revision.
|
|
*/
|
|
static char * __init kirkwood_id(void)
|
|
{
|
|
u32 dev, rev;
|
|
|
|
kirkwood_pcie_id(&dev, &rev);
|
|
|
|
if (dev == MV88F6281_DEV_ID) {
|
|
if (rev == MV88F6281_REV_Z0)
|
|
return "MV88F6281-Z0";
|
|
else if (rev == MV88F6281_REV_A0)
|
|
return "MV88F6281-A0";
|
|
else if (rev == MV88F6281_REV_A1)
|
|
return "MV88F6281-A1";
|
|
else
|
|
return "MV88F6281-Rev-Unsupported";
|
|
} else if (dev == MV88F6192_DEV_ID) {
|
|
if (rev == MV88F6192_REV_Z0)
|
|
return "MV88F6192-Z0";
|
|
else if (rev == MV88F6192_REV_A0)
|
|
return "MV88F6192-A0";
|
|
else
|
|
return "MV88F6192-Rev-Unsupported";
|
|
} else if (dev == MV88F6180_DEV_ID) {
|
|
if (rev == MV88F6180_REV_A0)
|
|
return "MV88F6180-Rev-A0";
|
|
else
|
|
return "MV88F6180-Rev-Unsupported";
|
|
} else {
|
|
return "Device-Unknown";
|
|
}
|
|
}
|
|
|
|
static void __init kirkwood_l2_init(void)
|
|
{
|
|
#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
|
|
writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
|
|
feroceon_l2_init(1);
|
|
#else
|
|
writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
|
|
feroceon_l2_init(0);
|
|
#endif
|
|
}
|
|
|
|
void __init kirkwood_init(void)
|
|
{
|
|
printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
|
|
kirkwood_id(), kirkwood_tclk);
|
|
kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
|
|
kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
|
|
kirkwood_spi_plat_data.tclk = kirkwood_tclk;
|
|
kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
|
|
kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
|
|
|
|
kirkwood_setup_cpu_mbus();
|
|
|
|
#ifdef CONFIG_CACHE_FEROCEON_L2
|
|
kirkwood_l2_init();
|
|
#endif
|
|
|
|
/* internal devices that every board has */
|
|
kirkwood_rtc_init();
|
|
kirkwood_wdt_init();
|
|
kirkwood_xor0_init();
|
|
kirkwood_xor1_init();
|
|
kirkwood_crypto_init();
|
|
}
|
|
|
|
static int __init kirkwood_clock_gate(void)
|
|
{
|
|
unsigned int curr = readl(CLOCK_GATING_CTRL);
|
|
|
|
printk(KERN_DEBUG "Gating clock of unused units\n");
|
|
printk(KERN_DEBUG "before: 0x%08x\n", curr);
|
|
|
|
/* Make sure those units are accessible */
|
|
writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
|
|
|
|
/* For SATA: first shutdown the phy */
|
|
if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
|
|
/* Disable PLL and IVREF */
|
|
writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
|
|
/* Disable PHY */
|
|
writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
|
|
}
|
|
if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
|
|
/* Disable PLL and IVREF */
|
|
writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
|
|
/* Disable PHY */
|
|
writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
|
|
}
|
|
|
|
/* For PCIe: first shutdown the phy */
|
|
if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
|
|
writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
|
|
while (1)
|
|
if (readl(PCIE_STATUS) & 0x1)
|
|
break;
|
|
writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
|
|
}
|
|
|
|
/* Now gate clock the required units */
|
|
writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
|
|
printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
|
|
|
|
return 0;
|
|
}
|
|
late_initcall(kirkwood_clock_gate);
|
|
|