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1333 lines
34 KiB
1333 lines
34 KiB
/* $Id: sunbmac.c,v 1.30 2002/01/15 06:48:55 davem Exp $
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* sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
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*
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* Copyright (C) 1997, 1998, 1999, 2003 David S. Miller (davem@redhat.com)
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/fcntl.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/in.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/crc32.h>
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#include <linux/errno.h>
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#include <linux/ethtool.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/bitops.h>
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#include <asm/auxio.h>
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#include <asm/byteorder.h>
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#include <asm/dma.h>
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#include <asm/idprom.h>
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#include <asm/io.h>
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#include <asm/openprom.h>
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#include <asm/oplib.h>
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#include <asm/pgtable.h>
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#include <asm/sbus.h>
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#include <asm/system.h>
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#include "sunbmac.h"
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#define DRV_NAME "sunbmac"
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#define DRV_VERSION "2.0"
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#define DRV_RELDATE "11/24/03"
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#define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
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static char version[] __initdata =
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DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
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MODULE_VERSION(DRV_VERSION);
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MODULE_AUTHOR(DRV_AUTHOR);
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MODULE_DESCRIPTION("Sun BigMAC 100baseT ethernet driver");
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MODULE_LICENSE("GPL");
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#undef DEBUG_PROBE
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#undef DEBUG_TX
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#undef DEBUG_IRQ
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#ifdef DEBUG_PROBE
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#define DP(x) printk x
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#else
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#define DP(x)
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#endif
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#ifdef DEBUG_TX
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#define DTX(x) printk x
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#else
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#define DTX(x)
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#endif
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#ifdef DEBUG_IRQ
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#define DIRQ(x) printk x
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#else
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#define DIRQ(x)
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#endif
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static struct bigmac *root_bigmac_dev;
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#define DEFAULT_JAMSIZE 4 /* Toe jam */
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#define QEC_RESET_TRIES 200
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static int qec_global_reset(void __iomem *gregs)
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{
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int tries = QEC_RESET_TRIES;
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sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
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while (--tries) {
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if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) {
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udelay(20);
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continue;
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}
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break;
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}
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if (tries)
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return 0;
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printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n");
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return -1;
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}
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static void qec_init(struct bigmac *bp)
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{
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void __iomem *gregs = bp->gregs;
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struct sbus_dev *qec_sdev = bp->qec_sdev;
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u8 bsizes = bp->bigmac_bursts;
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u32 regval;
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/* 64byte bursts do not work at the moment, do
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* not even try to enable them. -DaveM
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*/
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if (bsizes & DMA_BURST32)
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regval = GLOB_CTRL_B32;
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else
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regval = GLOB_CTRL_B16;
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sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL);
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sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE);
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/* All of memsize is given to bigmac. */
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sbus_writel(qec_sdev->reg_addrs[1].reg_size,
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gregs + GLOB_MSIZE);
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/* Half to the transmitter, half to the receiver. */
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sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
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gregs + GLOB_TSIZE);
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sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
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gregs + GLOB_RSIZE);
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}
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#define TX_RESET_TRIES 32
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#define RX_RESET_TRIES 32
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static void bigmac_tx_reset(void __iomem *bregs)
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{
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int tries = TX_RESET_TRIES;
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sbus_writel(0, bregs + BMAC_TXCFG);
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/* The fifo threshold bit is read-only and does
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* not clear. -DaveM
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*/
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while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 &&
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--tries != 0)
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udelay(20);
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if (!tries) {
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printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n");
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printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n",
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sbus_readl(bregs + BMAC_TXCFG));
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}
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}
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static void bigmac_rx_reset(void __iomem *bregs)
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{
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int tries = RX_RESET_TRIES;
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sbus_writel(0, bregs + BMAC_RXCFG);
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while (sbus_readl(bregs + BMAC_RXCFG) && --tries)
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udelay(20);
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if (!tries) {
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printk(KERN_ERR "BIGMAC: Receiver will not reset.\n");
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printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n",
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sbus_readl(bregs + BMAC_RXCFG));
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}
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}
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/* Reset the transmitter and receiver. */
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static void bigmac_stop(struct bigmac *bp)
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{
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bigmac_tx_reset(bp->bregs);
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bigmac_rx_reset(bp->bregs);
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}
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static void bigmac_get_counters(struct bigmac *bp, void __iomem *bregs)
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{
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struct net_device_stats *stats = &bp->enet_stats;
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stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR);
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sbus_writel(0, bregs + BMAC_RCRCECTR);
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stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR);
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sbus_writel(0, bregs + BMAC_UNALECTR);
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stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR);
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sbus_writel(0, bregs + BMAC_GLECTR);
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stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR);
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stats->collisions +=
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(sbus_readl(bregs + BMAC_EXCTR) +
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sbus_readl(bregs + BMAC_LTCTR));
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sbus_writel(0, bregs + BMAC_EXCTR);
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sbus_writel(0, bregs + BMAC_LTCTR);
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}
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static void bigmac_clean_rings(struct bigmac *bp)
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{
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int i;
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for (i = 0; i < RX_RING_SIZE; i++) {
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if (bp->rx_skbs[i] != NULL) {
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dev_kfree_skb_any(bp->rx_skbs[i]);
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bp->rx_skbs[i] = NULL;
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}
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}
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for (i = 0; i < TX_RING_SIZE; i++) {
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if (bp->tx_skbs[i] != NULL) {
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dev_kfree_skb_any(bp->tx_skbs[i]);
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bp->tx_skbs[i] = NULL;
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}
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}
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}
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static void bigmac_init_rings(struct bigmac *bp, int from_irq)
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{
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struct bmac_init_block *bb = bp->bmac_block;
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struct net_device *dev = bp->dev;
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int i, gfp_flags = GFP_KERNEL;
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if (from_irq || in_interrupt())
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gfp_flags = GFP_ATOMIC;
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bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0;
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/* Free any skippy bufs left around in the rings. */
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bigmac_clean_rings(bp);
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/* Now get new skbufs for the receive ring. */
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for (i = 0; i < RX_RING_SIZE; i++) {
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struct sk_buff *skb;
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skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
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if (!skb)
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continue;
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bp->rx_skbs[i] = skb;
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skb->dev = dev;
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/* Because we reserve afterwards. */
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skb_put(skb, ETH_FRAME_LEN);
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skb_reserve(skb, 34);
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bb->be_rxd[i].rx_addr =
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sbus_map_single(bp->bigmac_sdev, skb->data,
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RX_BUF_ALLOC_SIZE - 34,
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SBUS_DMA_FROMDEVICE);
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bb->be_rxd[i].rx_flags =
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(RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
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}
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for (i = 0; i < TX_RING_SIZE; i++)
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bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0;
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}
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#define MGMT_CLKON (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
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#define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
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static void idle_transceiver(void __iomem *tregs)
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{
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int i = 20;
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while (i--) {
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sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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}
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}
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static void write_tcvr_bit(struct bigmac *bp, void __iomem *tregs, int bit)
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{
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if (bp->tcvr_type == internal) {
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bit = (bit & 1) << 3;
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sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO),
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tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
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tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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} else if (bp->tcvr_type == external) {
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bit = (bit & 1) << 2;
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sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB,
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tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK,
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tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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} else {
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printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n");
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}
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}
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static int read_tcvr_bit(struct bigmac *bp, void __iomem *tregs)
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{
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int retval = 0;
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if (bp->tcvr_type == internal) {
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sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
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tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
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} else if (bp->tcvr_type == external) {
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sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
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} else {
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printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n");
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}
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return retval;
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}
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static int read_tcvr_bit2(struct bigmac *bp, void __iomem *tregs)
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{
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int retval = 0;
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if (bp->tcvr_type == internal) {
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sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
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sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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} else if (bp->tcvr_type == external) {
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sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
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sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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} else {
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printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n");
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}
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return retval;
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}
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static void put_tcvr_byte(struct bigmac *bp,
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void __iomem *tregs,
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unsigned int byte)
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{
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int shift = 4;
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do {
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write_tcvr_bit(bp, tregs, ((byte >> shift) & 1));
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shift -= 1;
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} while (shift >= 0);
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}
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static void bigmac_tcvr_write(struct bigmac *bp, void __iomem *tregs,
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int reg, unsigned short val)
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{
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int shift;
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reg &= 0xff;
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val &= 0xffff;
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switch(bp->tcvr_type) {
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case internal:
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case external:
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break;
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default:
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printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
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return;
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};
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idle_transceiver(tregs);
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write_tcvr_bit(bp, tregs, 0);
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write_tcvr_bit(bp, tregs, 1);
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write_tcvr_bit(bp, tregs, 0);
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write_tcvr_bit(bp, tregs, 1);
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put_tcvr_byte(bp, tregs,
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((bp->tcvr_type == internal) ?
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BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
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put_tcvr_byte(bp, tregs, reg);
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write_tcvr_bit(bp, tregs, 1);
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write_tcvr_bit(bp, tregs, 0);
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shift = 15;
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do {
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write_tcvr_bit(bp, tregs, (val >> shift) & 1);
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shift -= 1;
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} while (shift >= 0);
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}
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static unsigned short bigmac_tcvr_read(struct bigmac *bp,
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void __iomem *tregs,
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int reg)
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{
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unsigned short retval = 0;
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reg &= 0xff;
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switch(bp->tcvr_type) {
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case internal:
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case external:
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break;
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default:
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printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
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return 0xffff;
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};
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idle_transceiver(tregs);
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write_tcvr_bit(bp, tregs, 0);
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write_tcvr_bit(bp, tregs, 1);
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write_tcvr_bit(bp, tregs, 1);
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write_tcvr_bit(bp, tregs, 0);
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put_tcvr_byte(bp, tregs,
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((bp->tcvr_type == internal) ?
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BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
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put_tcvr_byte(bp, tregs, reg);
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if (bp->tcvr_type == external) {
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int shift = 15;
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(void) read_tcvr_bit2(bp, tregs);
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(void) read_tcvr_bit2(bp, tregs);
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do {
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int tmp;
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tmp = read_tcvr_bit2(bp, tregs);
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retval |= ((tmp & 1) << shift);
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shift -= 1;
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} while (shift >= 0);
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(void) read_tcvr_bit2(bp, tregs);
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(void) read_tcvr_bit2(bp, tregs);
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(void) read_tcvr_bit2(bp, tregs);
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} else {
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int shift = 15;
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(void) read_tcvr_bit(bp, tregs);
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(void) read_tcvr_bit(bp, tregs);
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do {
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int tmp;
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tmp = read_tcvr_bit(bp, tregs);
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retval |= ((tmp & 1) << shift);
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shift -= 1;
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} while (shift >= 0);
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(void) read_tcvr_bit(bp, tregs);
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(void) read_tcvr_bit(bp, tregs);
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(void) read_tcvr_bit(bp, tregs);
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}
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return retval;
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}
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static void bigmac_tcvr_init(struct bigmac *bp)
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{
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void __iomem *tregs = bp->tregs;
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u32 mpal;
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idle_transceiver(tregs);
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sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
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tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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/* Only the bit for the present transceiver (internal or
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* external) will stick, set them both and see what stays.
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*/
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sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
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sbus_readl(tregs + TCVR_MPAL);
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udelay(20);
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|
|
mpal = sbus_readl(tregs + TCVR_MPAL);
|
|
if (mpal & MGMT_PAL_EXT_MDIO) {
|
|
bp->tcvr_type = external;
|
|
sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
|
|
tregs + TCVR_TPAL);
|
|
sbus_readl(tregs + TCVR_TPAL);
|
|
} else if (mpal & MGMT_PAL_INT_MDIO) {
|
|
bp->tcvr_type = internal;
|
|
sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK |
|
|
TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
|
|
tregs + TCVR_TPAL);
|
|
sbus_readl(tregs + TCVR_TPAL);
|
|
} else {
|
|
printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor "
|
|
"external MDIO available!\n");
|
|
printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
|
|
sbus_readl(tregs + TCVR_MPAL),
|
|
sbus_readl(tregs + TCVR_TPAL));
|
|
}
|
|
}
|
|
|
|
static int bigmac_init(struct bigmac *, int);
|
|
|
|
static int try_next_permutation(struct bigmac *bp, void __iomem *tregs)
|
|
{
|
|
if (bp->sw_bmcr & BMCR_SPEED100) {
|
|
int timeout;
|
|
|
|
/* Reset the PHY. */
|
|
bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
|
|
bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
|
|
bp->sw_bmcr = (BMCR_RESET);
|
|
bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
|
|
|
|
timeout = 64;
|
|
while (--timeout) {
|
|
bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
|
|
if ((bp->sw_bmcr & BMCR_RESET) == 0)
|
|
break;
|
|
udelay(20);
|
|
}
|
|
if (timeout == 0)
|
|
printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
|
|
|
|
bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
|
|
|
|
/* Now we try 10baseT. */
|
|
bp->sw_bmcr &= ~(BMCR_SPEED100);
|
|
bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
|
|
return 0;
|
|
}
|
|
|
|
/* We've tried them all. */
|
|
return -1;
|
|
}
|
|
|
|
static void bigmac_timer(unsigned long data)
|
|
{
|
|
struct bigmac *bp = (struct bigmac *) data;
|
|
void __iomem *tregs = bp->tregs;
|
|
int restart_timer = 0;
|
|
|
|
bp->timer_ticks++;
|
|
if (bp->timer_state == ltrywait) {
|
|
bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
|
|
bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
|
|
if (bp->sw_bmsr & BMSR_LSTATUS) {
|
|
printk(KERN_INFO "%s: Link is now up at %s.\n",
|
|
bp->dev->name,
|
|
(bp->sw_bmcr & BMCR_SPEED100) ?
|
|
"100baseT" : "10baseT");
|
|
bp->timer_state = asleep;
|
|
restart_timer = 0;
|
|
} else {
|
|
if (bp->timer_ticks >= 4) {
|
|
int ret;
|
|
|
|
ret = try_next_permutation(bp, tregs);
|
|
if (ret == -1) {
|
|
printk(KERN_ERR "%s: Link down, cable problem?\n",
|
|
bp->dev->name);
|
|
ret = bigmac_init(bp, 0);
|
|
if (ret) {
|
|
printk(KERN_ERR "%s: Error, cannot re-init the "
|
|
"BigMAC.\n", bp->dev->name);
|
|
}
|
|
return;
|
|
}
|
|
bp->timer_ticks = 0;
|
|
restart_timer = 1;
|
|
} else {
|
|
restart_timer = 1;
|
|
}
|
|
}
|
|
} else {
|
|
/* Can't happens.... */
|
|
printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
|
|
bp->dev->name);
|
|
restart_timer = 0;
|
|
bp->timer_ticks = 0;
|
|
bp->timer_state = asleep; /* foo on you */
|
|
}
|
|
|
|
if (restart_timer != 0) {
|
|
bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
|
|
add_timer(&bp->bigmac_timer);
|
|
}
|
|
}
|
|
|
|
/* Well, really we just force the chip into 100baseT then
|
|
* 10baseT, each time checking for a link status.
|
|
*/
|
|
static void bigmac_begin_auto_negotiation(struct bigmac *bp)
|
|
{
|
|
void __iomem *tregs = bp->tregs;
|
|
int timeout;
|
|
|
|
/* Grab new software copies of PHY registers. */
|
|
bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
|
|
bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
|
|
|
|
/* Reset the PHY. */
|
|
bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
|
|
bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
|
|
bp->sw_bmcr = (BMCR_RESET);
|
|
bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
|
|
|
|
timeout = 64;
|
|
while (--timeout) {
|
|
bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
|
|
if ((bp->sw_bmcr & BMCR_RESET) == 0)
|
|
break;
|
|
udelay(20);
|
|
}
|
|
if (timeout == 0)
|
|
printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
|
|
|
|
bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
|
|
|
|
/* First we try 100baseT. */
|
|
bp->sw_bmcr |= BMCR_SPEED100;
|
|
bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
|
|
|
|
bp->timer_state = ltrywait;
|
|
bp->timer_ticks = 0;
|
|
bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10;
|
|
bp->bigmac_timer.data = (unsigned long) bp;
|
|
bp->bigmac_timer.function = &bigmac_timer;
|
|
add_timer(&bp->bigmac_timer);
|
|
}
|
|
|
|
static int bigmac_init(struct bigmac *bp, int from_irq)
|
|
{
|
|
void __iomem *gregs = bp->gregs;
|
|
void __iomem *cregs = bp->creg;
|
|
void __iomem *bregs = bp->bregs;
|
|
unsigned char *e = &bp->dev->dev_addr[0];
|
|
|
|
/* Latch current counters into statistics. */
|
|
bigmac_get_counters(bp, bregs);
|
|
|
|
/* Reset QEC. */
|
|
qec_global_reset(gregs);
|
|
|
|
/* Init QEC. */
|
|
qec_init(bp);
|
|
|
|
/* Alloc and reset the tx/rx descriptor chains. */
|
|
bigmac_init_rings(bp, from_irq);
|
|
|
|
/* Initialize the PHY. */
|
|
bigmac_tcvr_init(bp);
|
|
|
|
/* Stop transmitter and receiver. */
|
|
bigmac_stop(bp);
|
|
|
|
/* Set hardware ethernet address. */
|
|
sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2);
|
|
sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1);
|
|
sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0);
|
|
|
|
/* Clear the hash table until mc upload occurs. */
|
|
sbus_writel(0, bregs + BMAC_HTABLE3);
|
|
sbus_writel(0, bregs + BMAC_HTABLE2);
|
|
sbus_writel(0, bregs + BMAC_HTABLE1);
|
|
sbus_writel(0, bregs + BMAC_HTABLE0);
|
|
|
|
/* Enable Big Mac hash table filter. */
|
|
sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO,
|
|
bregs + BMAC_RXCFG);
|
|
udelay(20);
|
|
|
|
/* Ok, configure the Big Mac transmitter. */
|
|
sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG);
|
|
|
|
/* The HME docs recommend to use the 10LSB of our MAC here. */
|
|
sbus_writel(((e[5] | e[4] << 8) & 0x3ff),
|
|
bregs + BMAC_RSEED);
|
|
|
|
/* Enable the output drivers no matter what. */
|
|
sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV,
|
|
bregs + BMAC_XIFCFG);
|
|
|
|
/* Tell the QEC where the ring descriptors are. */
|
|
sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0),
|
|
cregs + CREG_RXDS);
|
|
sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0),
|
|
cregs + CREG_TXDS);
|
|
|
|
/* Setup the FIFO pointers into QEC local memory. */
|
|
sbus_writel(0, cregs + CREG_RXRBUFPTR);
|
|
sbus_writel(0, cregs + CREG_RXWBUFPTR);
|
|
sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
|
|
cregs + CREG_TXRBUFPTR);
|
|
sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
|
|
cregs + CREG_TXWBUFPTR);
|
|
|
|
/* Tell bigmac what interrupts we don't want to hear about. */
|
|
sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME,
|
|
bregs + BMAC_IMASK);
|
|
|
|
/* Enable the various other irq's. */
|
|
sbus_writel(0, cregs + CREG_RIMASK);
|
|
sbus_writel(0, cregs + CREG_TIMASK);
|
|
sbus_writel(0, cregs + CREG_QMASK);
|
|
sbus_writel(0, cregs + CREG_BMASK);
|
|
|
|
/* Set jam size to a reasonable default. */
|
|
sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE);
|
|
|
|
/* Clear collision counter. */
|
|
sbus_writel(0, cregs + CREG_CCNT);
|
|
|
|
/* Enable transmitter and receiver. */
|
|
sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE,
|
|
bregs + BMAC_TXCFG);
|
|
sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE,
|
|
bregs + BMAC_RXCFG);
|
|
|
|
/* Ok, start detecting link speed/duplex. */
|
|
bigmac_begin_auto_negotiation(bp);
|
|
|
|
/* Success. */
|
|
return 0;
|
|
}
|
|
|
|
/* Error interrupts get sent here. */
|
|
static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status)
|
|
{
|
|
printk(KERN_ERR "bigmac_is_medium_rare: ");
|
|
if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) {
|
|
if (qec_status & GLOB_STAT_ER)
|
|
printk("QEC_ERROR, ");
|
|
if (qec_status & GLOB_STAT_BM)
|
|
printk("QEC_BMAC_ERROR, ");
|
|
}
|
|
if (bmac_status & CREG_STAT_ERRORS) {
|
|
if (bmac_status & CREG_STAT_BERROR)
|
|
printk("BMAC_ERROR, ");
|
|
if (bmac_status & CREG_STAT_TXDERROR)
|
|
printk("TXD_ERROR, ");
|
|
if (bmac_status & CREG_STAT_TXLERR)
|
|
printk("TX_LATE_ERROR, ");
|
|
if (bmac_status & CREG_STAT_TXPERR)
|
|
printk("TX_PARITY_ERROR, ");
|
|
if (bmac_status & CREG_STAT_TXSERR)
|
|
printk("TX_SBUS_ERROR, ");
|
|
|
|
if (bmac_status & CREG_STAT_RXDROP)
|
|
printk("RX_DROP_ERROR, ");
|
|
|
|
if (bmac_status & CREG_STAT_RXSMALL)
|
|
printk("RX_SMALL_ERROR, ");
|
|
if (bmac_status & CREG_STAT_RXLERR)
|
|
printk("RX_LATE_ERROR, ");
|
|
if (bmac_status & CREG_STAT_RXPERR)
|
|
printk("RX_PARITY_ERROR, ");
|
|
if (bmac_status & CREG_STAT_RXSERR)
|
|
printk("RX_SBUS_ERROR, ");
|
|
}
|
|
|
|
printk(" RESET\n");
|
|
bigmac_init(bp, 1);
|
|
}
|
|
|
|
/* BigMAC transmit complete service routines. */
|
|
static void bigmac_tx(struct bigmac *bp)
|
|
{
|
|
struct be_txd *txbase = &bp->bmac_block->be_txd[0];
|
|
struct net_device *dev = bp->dev;
|
|
int elem;
|
|
|
|
spin_lock(&bp->lock);
|
|
|
|
elem = bp->tx_old;
|
|
DTX(("bigmac_tx: tx_old[%d] ", elem));
|
|
while (elem != bp->tx_new) {
|
|
struct sk_buff *skb;
|
|
struct be_txd *this = &txbase[elem];
|
|
|
|
DTX(("this(%p) [flags(%08x)addr(%08x)]",
|
|
this, this->tx_flags, this->tx_addr));
|
|
|
|
if (this->tx_flags & TXD_OWN)
|
|
break;
|
|
skb = bp->tx_skbs[elem];
|
|
bp->enet_stats.tx_packets++;
|
|
bp->enet_stats.tx_bytes += skb->len;
|
|
sbus_unmap_single(bp->bigmac_sdev,
|
|
this->tx_addr, skb->len,
|
|
SBUS_DMA_TODEVICE);
|
|
|
|
DTX(("skb(%p) ", skb));
|
|
bp->tx_skbs[elem] = NULL;
|
|
dev_kfree_skb_irq(skb);
|
|
|
|
elem = NEXT_TX(elem);
|
|
}
|
|
DTX((" DONE, tx_old=%d\n", elem));
|
|
bp->tx_old = elem;
|
|
|
|
if (netif_queue_stopped(dev) &&
|
|
TX_BUFFS_AVAIL(bp) > 0)
|
|
netif_wake_queue(bp->dev);
|
|
|
|
spin_unlock(&bp->lock);
|
|
}
|
|
|
|
/* BigMAC receive complete service routines. */
|
|
static void bigmac_rx(struct bigmac *bp)
|
|
{
|
|
struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0];
|
|
struct be_rxd *this;
|
|
int elem = bp->rx_new, drops = 0;
|
|
u32 flags;
|
|
|
|
this = &rxbase[elem];
|
|
while (!((flags = this->rx_flags) & RXD_OWN)) {
|
|
struct sk_buff *skb;
|
|
int len = (flags & RXD_LENGTH); /* FCS not included */
|
|
|
|
/* Check for errors. */
|
|
if (len < ETH_ZLEN) {
|
|
bp->enet_stats.rx_errors++;
|
|
bp->enet_stats.rx_length_errors++;
|
|
|
|
drop_it:
|
|
/* Return it to the BigMAC. */
|
|
bp->enet_stats.rx_dropped++;
|
|
this->rx_flags =
|
|
(RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
|
|
goto next;
|
|
}
|
|
skb = bp->rx_skbs[elem];
|
|
if (len > RX_COPY_THRESHOLD) {
|
|
struct sk_buff *new_skb;
|
|
|
|
/* Now refill the entry, if we can. */
|
|
new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
|
|
if (new_skb == NULL) {
|
|
drops++;
|
|
goto drop_it;
|
|
}
|
|
sbus_unmap_single(bp->bigmac_sdev,
|
|
this->rx_addr,
|
|
RX_BUF_ALLOC_SIZE - 34,
|
|
SBUS_DMA_FROMDEVICE);
|
|
bp->rx_skbs[elem] = new_skb;
|
|
new_skb->dev = bp->dev;
|
|
skb_put(new_skb, ETH_FRAME_LEN);
|
|
skb_reserve(new_skb, 34);
|
|
this->rx_addr = sbus_map_single(bp->bigmac_sdev,
|
|
new_skb->data,
|
|
RX_BUF_ALLOC_SIZE - 34,
|
|
SBUS_DMA_FROMDEVICE);
|
|
this->rx_flags =
|
|
(RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
|
|
|
|
/* Trim the original skb for the netif. */
|
|
skb_trim(skb, len);
|
|
} else {
|
|
struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
|
|
|
|
if (copy_skb == NULL) {
|
|
drops++;
|
|
goto drop_it;
|
|
}
|
|
copy_skb->dev = bp->dev;
|
|
skb_reserve(copy_skb, 2);
|
|
skb_put(copy_skb, len);
|
|
sbus_dma_sync_single_for_cpu(bp->bigmac_sdev,
|
|
this->rx_addr, len,
|
|
SBUS_DMA_FROMDEVICE);
|
|
eth_copy_and_sum(copy_skb, (unsigned char *)skb->data, len, 0);
|
|
sbus_dma_sync_single_for_device(bp->bigmac_sdev,
|
|
this->rx_addr, len,
|
|
SBUS_DMA_FROMDEVICE);
|
|
|
|
/* Reuse original ring buffer. */
|
|
this->rx_flags =
|
|
(RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
|
|
|
|
skb = copy_skb;
|
|
}
|
|
|
|
/* No checksums done by the BigMAC ;-( */
|
|
skb->protocol = eth_type_trans(skb, bp->dev);
|
|
netif_rx(skb);
|
|
bp->dev->last_rx = jiffies;
|
|
bp->enet_stats.rx_packets++;
|
|
bp->enet_stats.rx_bytes += len;
|
|
next:
|
|
elem = NEXT_RX(elem);
|
|
this = &rxbase[elem];
|
|
}
|
|
bp->rx_new = elem;
|
|
if (drops)
|
|
printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name);
|
|
}
|
|
|
|
static irqreturn_t bigmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
struct bigmac *bp = (struct bigmac *) dev_id;
|
|
u32 qec_status, bmac_status;
|
|
|
|
DIRQ(("bigmac_interrupt: "));
|
|
|
|
/* Latch status registers now. */
|
|
bmac_status = sbus_readl(bp->creg + CREG_STAT);
|
|
qec_status = sbus_readl(bp->gregs + GLOB_STAT);
|
|
|
|
DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status));
|
|
if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) ||
|
|
(bmac_status & CREG_STAT_ERRORS))
|
|
bigmac_is_medium_rare(bp, qec_status, bmac_status);
|
|
|
|
if (bmac_status & CREG_STAT_TXIRQ)
|
|
bigmac_tx(bp);
|
|
|
|
if (bmac_status & CREG_STAT_RXIRQ)
|
|
bigmac_rx(bp);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int bigmac_open(struct net_device *dev)
|
|
{
|
|
struct bigmac *bp = (struct bigmac *) dev->priv;
|
|
int ret;
|
|
|
|
ret = request_irq(dev->irq, &bigmac_interrupt, SA_SHIRQ, dev->name, bp);
|
|
if (ret) {
|
|
printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq);
|
|
return ret;
|
|
}
|
|
init_timer(&bp->bigmac_timer);
|
|
ret = bigmac_init(bp, 0);
|
|
if (ret)
|
|
free_irq(dev->irq, bp);
|
|
return ret;
|
|
}
|
|
|
|
static int bigmac_close(struct net_device *dev)
|
|
{
|
|
struct bigmac *bp = (struct bigmac *) dev->priv;
|
|
|
|
del_timer(&bp->bigmac_timer);
|
|
bp->timer_state = asleep;
|
|
bp->timer_ticks = 0;
|
|
|
|
bigmac_stop(bp);
|
|
bigmac_clean_rings(bp);
|
|
free_irq(dev->irq, bp);
|
|
return 0;
|
|
}
|
|
|
|
static void bigmac_tx_timeout(struct net_device *dev)
|
|
{
|
|
struct bigmac *bp = (struct bigmac *) dev->priv;
|
|
|
|
bigmac_init(bp, 0);
|
|
netif_wake_queue(dev);
|
|
}
|
|
|
|
/* Put a packet on the wire. */
|
|
static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
{
|
|
struct bigmac *bp = (struct bigmac *) dev->priv;
|
|
int len, entry;
|
|
u32 mapping;
|
|
|
|
len = skb->len;
|
|
mapping = sbus_map_single(bp->bigmac_sdev, skb->data, len, SBUS_DMA_TODEVICE);
|
|
|
|
/* Avoid a race... */
|
|
spin_lock_irq(&bp->lock);
|
|
entry = bp->tx_new;
|
|
DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry));
|
|
bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE;
|
|
bp->tx_skbs[entry] = skb;
|
|
bp->bmac_block->be_txd[entry].tx_addr = mapping;
|
|
bp->bmac_block->be_txd[entry].tx_flags =
|
|
(TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
|
|
bp->tx_new = NEXT_TX(entry);
|
|
if (TX_BUFFS_AVAIL(bp) <= 0)
|
|
netif_stop_queue(dev);
|
|
spin_unlock_irq(&bp->lock);
|
|
|
|
/* Get it going. */
|
|
sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL);
|
|
|
|
|
|
dev->trans_start = jiffies;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct net_device_stats *bigmac_get_stats(struct net_device *dev)
|
|
{
|
|
struct bigmac *bp = (struct bigmac *) dev->priv;
|
|
|
|
bigmac_get_counters(bp, bp->bregs);
|
|
return &bp->enet_stats;
|
|
}
|
|
|
|
static void bigmac_set_multicast(struct net_device *dev)
|
|
{
|
|
struct bigmac *bp = (struct bigmac *) dev->priv;
|
|
void __iomem *bregs = bp->bregs;
|
|
struct dev_mc_list *dmi = dev->mc_list;
|
|
char *addrs;
|
|
int i;
|
|
u32 tmp, crc;
|
|
|
|
/* Disable the receiver. The bit self-clears when
|
|
* the operation is complete.
|
|
*/
|
|
tmp = sbus_readl(bregs + BMAC_RXCFG);
|
|
tmp &= ~(BIGMAC_RXCFG_ENABLE);
|
|
sbus_writel(tmp, bregs + BMAC_RXCFG);
|
|
while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0)
|
|
udelay(20);
|
|
|
|
if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
|
|
sbus_writel(0xffff, bregs + BMAC_HTABLE0);
|
|
sbus_writel(0xffff, bregs + BMAC_HTABLE1);
|
|
sbus_writel(0xffff, bregs + BMAC_HTABLE2);
|
|
sbus_writel(0xffff, bregs + BMAC_HTABLE3);
|
|
} else if (dev->flags & IFF_PROMISC) {
|
|
tmp = sbus_readl(bregs + BMAC_RXCFG);
|
|
tmp |= BIGMAC_RXCFG_PMISC;
|
|
sbus_writel(tmp, bregs + BMAC_RXCFG);
|
|
} else {
|
|
u16 hash_table[4];
|
|
|
|
for (i = 0; i < 4; i++)
|
|
hash_table[i] = 0;
|
|
|
|
for (i = 0; i < dev->mc_count; i++) {
|
|
addrs = dmi->dmi_addr;
|
|
dmi = dmi->next;
|
|
|
|
if (!(*addrs & 1))
|
|
continue;
|
|
|
|
crc = ether_crc_le(6, addrs);
|
|
crc >>= 26;
|
|
hash_table[crc >> 4] |= 1 << (crc & 0xf);
|
|
}
|
|
sbus_writel(hash_table[0], bregs + BMAC_HTABLE0);
|
|
sbus_writel(hash_table[1], bregs + BMAC_HTABLE1);
|
|
sbus_writel(hash_table[2], bregs + BMAC_HTABLE2);
|
|
sbus_writel(hash_table[3], bregs + BMAC_HTABLE3);
|
|
}
|
|
|
|
/* Re-enable the receiver. */
|
|
tmp = sbus_readl(bregs + BMAC_RXCFG);
|
|
tmp |= BIGMAC_RXCFG_ENABLE;
|
|
sbus_writel(tmp, bregs + BMAC_RXCFG);
|
|
}
|
|
|
|
/* Ethtool support... */
|
|
static void bigmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
|
|
{
|
|
struct bigmac *bp = dev->priv;
|
|
|
|
strcpy(info->driver, "sunbmac");
|
|
strcpy(info->version, "2.0");
|
|
sprintf(info->bus_info, "SBUS:%d",
|
|
bp->qec_sdev->slot);
|
|
}
|
|
|
|
static u32 bigmac_get_link(struct net_device *dev)
|
|
{
|
|
struct bigmac *bp = dev->priv;
|
|
|
|
spin_lock_irq(&bp->lock);
|
|
bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, BIGMAC_BMSR);
|
|
spin_unlock_irq(&bp->lock);
|
|
|
|
return (bp->sw_bmsr & BMSR_LSTATUS);
|
|
}
|
|
|
|
static struct ethtool_ops bigmac_ethtool_ops = {
|
|
.get_drvinfo = bigmac_get_drvinfo,
|
|
.get_link = bigmac_get_link,
|
|
};
|
|
|
|
static int __init bigmac_ether_init(struct sbus_dev *qec_sdev)
|
|
{
|
|
struct net_device *dev;
|
|
static int version_printed;
|
|
struct bigmac *bp;
|
|
u8 bsizes, bsizes_more;
|
|
int i;
|
|
|
|
/* Get a new device struct for this interface. */
|
|
dev = alloc_etherdev(sizeof(struct bigmac));
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
SET_MODULE_OWNER(dev);
|
|
|
|
if (version_printed++ == 0)
|
|
printk(KERN_INFO "%s", version);
|
|
|
|
dev->base_addr = (long) qec_sdev;
|
|
for (i = 0; i < 6; i++)
|
|
dev->dev_addr[i] = idprom->id_ethaddr[i];
|
|
|
|
/* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
|
|
bp = dev->priv;
|
|
bp->qec_sdev = qec_sdev;
|
|
bp->bigmac_sdev = qec_sdev->child;
|
|
|
|
spin_lock_init(&bp->lock);
|
|
|
|
/* Verify the registers we expect, are actually there. */
|
|
if ((bp->bigmac_sdev->num_registers != 3) ||
|
|
(bp->qec_sdev->num_registers != 2)) {
|
|
printk(KERN_ERR "BIGMAC: Device does not have 2 and 3 regs, it has %d and %d.\n",
|
|
bp->qec_sdev->num_registers,
|
|
bp->bigmac_sdev->num_registers);
|
|
printk(KERN_ERR "BIGMAC: Would you like that for here or to go?\n");
|
|
goto fail_and_cleanup;
|
|
}
|
|
|
|
/* Map in QEC global control registers. */
|
|
bp->gregs = sbus_ioremap(&bp->qec_sdev->resource[0], 0,
|
|
GLOB_REG_SIZE, "BigMAC QEC GLobal Regs");
|
|
if (!bp->gregs) {
|
|
printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n");
|
|
goto fail_and_cleanup;
|
|
}
|
|
|
|
/* Make sure QEC is in BigMAC mode. */
|
|
if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) {
|
|
printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
|
|
goto fail_and_cleanup;
|
|
}
|
|
|
|
/* Reset the QEC. */
|
|
if (qec_global_reset(bp->gregs))
|
|
goto fail_and_cleanup;
|
|
|
|
/* Get supported SBUS burst sizes. */
|
|
bsizes = prom_getintdefault(bp->qec_sdev->prom_node,
|
|
"burst-sizes",
|
|
0xff);
|
|
|
|
bsizes_more = prom_getintdefault(bp->qec_sdev->bus->prom_node,
|
|
"burst-sizes",
|
|
0xff);
|
|
|
|
bsizes &= 0xff;
|
|
if (bsizes_more != 0xff)
|
|
bsizes &= bsizes_more;
|
|
if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
|
|
(bsizes & DMA_BURST32) == 0)
|
|
bsizes = (DMA_BURST32 - 1);
|
|
bp->bigmac_bursts = bsizes;
|
|
|
|
/* Perform QEC initialization. */
|
|
qec_init(bp);
|
|
|
|
/* Map in the BigMAC channel registers. */
|
|
bp->creg = sbus_ioremap(&bp->bigmac_sdev->resource[0], 0,
|
|
CREG_REG_SIZE, "BigMAC QEC Channel Regs");
|
|
if (!bp->creg) {
|
|
printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n");
|
|
goto fail_and_cleanup;
|
|
}
|
|
|
|
/* Map in the BigMAC control registers. */
|
|
bp->bregs = sbus_ioremap(&bp->bigmac_sdev->resource[1], 0,
|
|
BMAC_REG_SIZE, "BigMAC Primary Regs");
|
|
if (!bp->bregs) {
|
|
printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n");
|
|
goto fail_and_cleanup;
|
|
}
|
|
|
|
/* Map in the BigMAC transceiver registers, this is how you poke at
|
|
* the BigMAC's PHY.
|
|
*/
|
|
bp->tregs = sbus_ioremap(&bp->bigmac_sdev->resource[2], 0,
|
|
TCVR_REG_SIZE, "BigMAC Transceiver Regs");
|
|
if (!bp->tregs) {
|
|
printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n");
|
|
goto fail_and_cleanup;
|
|
}
|
|
|
|
/* Stop the BigMAC. */
|
|
bigmac_stop(bp);
|
|
|
|
/* Allocate transmit/receive descriptor DVMA block. */
|
|
bp->bmac_block = sbus_alloc_consistent(bp->bigmac_sdev,
|
|
PAGE_SIZE,
|
|
&bp->bblock_dvma);
|
|
if (bp->bmac_block == NULL || bp->bblock_dvma == 0) {
|
|
printk(KERN_ERR "BIGMAC: Cannot allocate consistent DMA.\n");
|
|
goto fail_and_cleanup;
|
|
}
|
|
|
|
/* Get the board revision of this BigMAC. */
|
|
bp->board_rev = prom_getintdefault(bp->bigmac_sdev->prom_node,
|
|
"board-version", 1);
|
|
|
|
/* Init auto-negotiation timer state. */
|
|
init_timer(&bp->bigmac_timer);
|
|
bp->timer_state = asleep;
|
|
bp->timer_ticks = 0;
|
|
|
|
/* Backlink to generic net device struct. */
|
|
bp->dev = dev;
|
|
|
|
/* Set links to our BigMAC open and close routines. */
|
|
dev->open = &bigmac_open;
|
|
dev->stop = &bigmac_close;
|
|
dev->hard_start_xmit = &bigmac_start_xmit;
|
|
dev->ethtool_ops = &bigmac_ethtool_ops;
|
|
|
|
/* Set links to BigMAC statistic and multi-cast loading code. */
|
|
dev->get_stats = &bigmac_get_stats;
|
|
dev->set_multicast_list = &bigmac_set_multicast;
|
|
|
|
dev->tx_timeout = &bigmac_tx_timeout;
|
|
dev->watchdog_timeo = 5*HZ;
|
|
|
|
/* Finish net device registration. */
|
|
dev->irq = bp->bigmac_sdev->irqs[0];
|
|
dev->dma = 0;
|
|
|
|
if (register_netdev(dev)) {
|
|
printk(KERN_ERR "BIGMAC: Cannot register device.\n");
|
|
goto fail_and_cleanup;
|
|
}
|
|
|
|
/* Put us into the list of instances attached for later driver
|
|
* exit.
|
|
*/
|
|
bp->next_module = root_bigmac_dev;
|
|
root_bigmac_dev = bp;
|
|
|
|
printk(KERN_INFO "%s: BigMAC 100baseT Ethernet ", dev->name);
|
|
for (i = 0; i < 6; i++)
|
|
printk("%2.2x%c", dev->dev_addr[i],
|
|
i == 5 ? ' ' : ':');
|
|
printk("\n");
|
|
|
|
return 0;
|
|
|
|
fail_and_cleanup:
|
|
/* Something went wrong, undo whatever we did so far. */
|
|
/* Free register mappings if any. */
|
|
if (bp->gregs)
|
|
sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
|
|
if (bp->creg)
|
|
sbus_iounmap(bp->creg, CREG_REG_SIZE);
|
|
if (bp->bregs)
|
|
sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
|
|
if (bp->tregs)
|
|
sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
|
|
|
|
if (bp->bmac_block)
|
|
sbus_free_consistent(bp->bigmac_sdev,
|
|
PAGE_SIZE,
|
|
bp->bmac_block,
|
|
bp->bblock_dvma);
|
|
|
|
/* This also frees the co-located 'dev->priv' */
|
|
free_netdev(dev);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* QEC can be the parent of either QuadEthernet or
|
|
* a BigMAC. We want the latter.
|
|
*/
|
|
static int __init bigmac_match(struct sbus_dev *sdev)
|
|
{
|
|
struct sbus_dev *child = sdev->child;
|
|
|
|
if (strcmp(sdev->prom_name, "qec") != 0)
|
|
return 0;
|
|
|
|
if (child == NULL)
|
|
return 0;
|
|
|
|
if (strcmp(child->prom_name, "be") != 0)
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int __init bigmac_probe(void)
|
|
{
|
|
struct sbus_bus *sbus;
|
|
struct sbus_dev *sdev = NULL;
|
|
static int called;
|
|
int cards = 0, v;
|
|
|
|
root_bigmac_dev = NULL;
|
|
|
|
if (called)
|
|
return -ENODEV;
|
|
called++;
|
|
|
|
for_each_sbus(sbus) {
|
|
for_each_sbusdev(sdev, sbus) {
|
|
if (bigmac_match(sdev)) {
|
|
cards++;
|
|
if ((v = bigmac_ether_init(sdev)))
|
|
return v;
|
|
}
|
|
}
|
|
}
|
|
if (!cards)
|
|
return -ENODEV;
|
|
return 0;
|
|
}
|
|
|
|
static void __exit bigmac_cleanup(void)
|
|
{
|
|
while (root_bigmac_dev) {
|
|
struct bigmac *bp = root_bigmac_dev;
|
|
struct bigmac *bp_nxt = root_bigmac_dev->next_module;
|
|
|
|
sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
|
|
sbus_iounmap(bp->creg, CREG_REG_SIZE);
|
|
sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
|
|
sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
|
|
sbus_free_consistent(bp->bigmac_sdev,
|
|
PAGE_SIZE,
|
|
bp->bmac_block,
|
|
bp->bblock_dvma);
|
|
|
|
unregister_netdev(bp->dev);
|
|
free_netdev(bp->dev);
|
|
root_bigmac_dev = bp_nxt;
|
|
}
|
|
}
|
|
|
|
module_init(bigmac_probe);
|
|
module_exit(bigmac_cleanup);
|
|
|