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355 lines
11 KiB
355 lines
11 KiB
/*
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* linux/include/asm-arm/arch-clps711x/hardware.h
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*
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* This file contains the hardware definitions of the Prospector P720T.
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*
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <linux/config.h>
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#define CLPS7111_VIRT_BASE 0xff000000
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#define CLPS7111_BASE CLPS7111_VIRT_BASE
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/*
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* The physical addresses that the external chip select signals map to is
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* dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
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* processors. CONFIG_EP72XX_BOOT_ROM is only available if these
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* processors are in use.
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*/
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#ifndef CONFIG_EP72XX_ROM_BOOT
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#define CS0_PHYS_BASE (0x00000000)
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#define CS1_PHYS_BASE (0x10000000)
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#define CS2_PHYS_BASE (0x20000000)
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#define CS3_PHYS_BASE (0x30000000)
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#define CS4_PHYS_BASE (0x40000000)
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#define CS5_PHYS_BASE (0x50000000)
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#define CS6_PHYS_BASE (0x60000000)
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#define CS7_PHYS_BASE (0x70000000)
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#else
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#define CS0_PHYS_BASE (0x70000000)
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#define CS1_PHYS_BASE (0x60000000)
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#define CS2_PHYS_BASE (0x50000000)
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#define CS3_PHYS_BASE (0x40000000)
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#define CS4_PHYS_BASE (0x30000000)
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#define CS5_PHYS_BASE (0x20000000)
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#define CS6_PHYS_BASE (0x10000000)
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#define CS7_PHYS_BASE (0x00000000)
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#endif
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#if defined (CONFIG_ARCH_EP7211)
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#define EP7211_VIRT_BASE CLPS7111_VIRT_BASE
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#define EP7211_BASE CLPS7111_VIRT_BASE
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#include <asm/hardware/ep7211.h>
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#elif defined (CONFIG_ARCH_EP7212)
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#define EP7212_VIRT_BASE CLPS7111_VIRT_BASE
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#define EP7212_BASE CLPS7111_VIRT_BASE
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#include <asm/hardware/ep7212.h>
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#endif
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#define SYSPLD_VIRT_BASE 0xfe000000
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#define SYSPLD_BASE SYSPLD_VIRT_BASE
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#ifndef __ASSEMBLER__
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#define PCIO_BASE IO_BASE
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#endif
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#if defined (CONFIG_ARCH_AUTCPU12)
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#define CS89712_VIRT_BASE CLPS7111_VIRT_BASE
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#define CS89712_BASE CLPS7111_VIRT_BASE
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#include <asm/hardware/clps7111.h>
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#include <asm/hardware/ep7212.h>
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#include <asm/hardware/cs89712.h>
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#endif
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#if defined (CONFIG_ARCH_CDB89712)
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#include <asm/hardware/clps7111.h>
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#include <asm/hardware/ep7212.h>
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#include <asm/hardware/cs89712.h>
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/* dynamic ioremap() areas */
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#define FLASH_START 0x00000000
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#define FLASH_SIZE 0x800000
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#define FLASH_WIDTH 4
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#define SRAM_START 0x60000000
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#define SRAM_SIZE 0xc000
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#define SRAM_WIDTH 4
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#define BOOTROM_START 0x70000000
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#define BOOTROM_SIZE 0x80
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#define BOOTROM_WIDTH 4
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/* static cdb89712_map_io() areas */
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#define REGISTER_START 0x80000000
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#define REGISTER_SIZE 0x4000
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#define REGISTER_BASE 0xff000000
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#define ETHER_START 0x20000000
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#define ETHER_SIZE 0x1000
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#define ETHER_BASE 0xfe000000
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#endif
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#if defined (CONFIG_ARCH_EDB7211)
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/*
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* The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3)
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* and repeat across it. This is the mapping for it.
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*
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* In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
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* was cause for much consternation and headscratching. This should probably
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* be made a compile/run time kernel option.
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*/
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#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */
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#define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */
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/*
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* The CS8900A ethernet chip has its I/O registers wired to chip select 2
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* (nCS2). This is the mapping for it.
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*
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* In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
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* was cause for much consternation and headscratching. This should probably
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* be made a compile/run time kernel option.
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*/
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#define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */
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#define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */
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/*
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* The two flash banks are wired to chip selects 0 and 1. This is the mapping
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* for them.
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*
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* nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
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* in jumpered boot mode.
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*/
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#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
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#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
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#define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */
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#define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */
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#endif /* CONFIG_ARCH_EDB7211 */
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/*
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* Relevant bits in port D, which controls power to the various parts of
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* the LCD on the EDB7211.
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*/
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#define EDB_PD1_LCD_DC_DC_EN (1<<1)
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#define EDB_PD2_LCDEN (1<<2)
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#define EDB_PD3_LCDBL (1<<3)
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#if defined (CONFIG_ARCH_CEIVA)
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#define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE
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#define CEIVA_BASE CLPS7111_VIRT_BASE
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#include <asm/hardware/clps7111.h>
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#include <asm/hardware/ep7212.h>
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/*
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* The two flash banks are wired to chip selects 0 and 1. This is the mapping
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* for them.
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*
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* nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
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* in jumpered boot mode.
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*/
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#define CEIVA_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
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#define CEIVA_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
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#define CEIVA_VIRT_FLASH1 (0xfa000000) /* virtual */
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#define CEIVA_VIRT_FLASH2 (0xfb000000) /* virtual */
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#define CEIVA_FLASH_SIZE 0x100000
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#define CEIVA_FLASH_WIDTH 2
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#define SRAM_START 0x60000000
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#define SRAM_SIZE 0xc000
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#define SRAM_WIDTH 4
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#define BOOTROM_START 0x70000000
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#define BOOTROM_SIZE 0x80
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#define BOOTROM_WIDTH 4
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/*
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* SED1355 LCD controller
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*/
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#define CEIVA_PHYS_SED1355 CS2_PHYS_BASE
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#define CEIVA_VIRT_SED1355 (0xfc000000)
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/*
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* Relevant bits in port D, which controls power to the various parts of
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* the LCD on the Ceiva Photo Max, and reset to the LCD controller.
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*/
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// Reset line to SED1355 (must be high to operate)
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#define CEIVA_PD1_LCDRST (1<<1)
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// LCD panel enable (set to one, to enable LCD)
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#define CEIVA_PD4_LCDEN (1<<4)
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// Backlight (set to one, to turn on backlight
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#define CEIVA_PD5_LCDBL (1<<5)
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/*
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* Relevant bits in port B, which report the status of the buttons.
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*/
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// White button
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#define CEIVA_PB4_WHT_BTN (1<<4)
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// Black button
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#define CEIVA_PB0_BLK_BTN (1<<0)
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#endif // #if defined (CONFIG_ARCH_CEIVA)
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#if defined (CONFIG_MACH_MP1000)
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/* NOR FLASH */
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#define MP1000_NIO_BASE 0xf9000000 /* virtual */
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#define MP1000_NIO_START CS0_PHYS_BASE /* physical */
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#define MP1000_NIO_SIZE 0x00400000
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/* DSP Interface */
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#define MP1000_DSP_BASE 0xfa000000 /* virtual */
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#define MP1000_DSP_START CS1_PHYS_BASE /* physical */
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#define MP1000_DSP_SIZE 0x00100000
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/* LCD, DAA/DSP, RTC, DAA RW Reg all in CS2 */
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#define MP1000_LIO_BASE 0xfb000000 /* virtual */
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#define MP1000_LIO_START CS2_PHYS_BASE /* physical */
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#define MP1000_LIO_SIZE 0x00100000
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/* NAND FLASH */
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#define MP1000_FIO_BASE 0xfc000000 /* virtual */
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#define MP1000_FIO_START CS3_PHYS_BASE /* physical */
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#define MP1000_FIO_SIZE 0x00800000
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/* Ethernet */
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#define MP1000_EIO_BASE 0xfd000000 /* virtual */
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#define MP1000_EIO_START CS4_PHYS_BASE /* physical */
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#define MP1000_EIO_SIZE 0x00100000
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#define MP1000_LCD_OFFSET 0x00000000 /* LCD offset in CS2 */
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#define MP1000_DDD_OFFSET 0x00001000 /* DAA/DAI/DSP sft reset offst*/
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#define MP1000_RTC_OFFSET 0x00002000 /* RTC offset in CS2 */
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#define MP1000_DAA_OFFSET 0x00003000 /* DAA RW reg offset in CS2 */
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/* IDE */
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#define MP1000_IDE_BASE 0xfe000000 /* virtual */
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#define MP1000_IDE_START CS5_PHYS_BASE /* physical */
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#define MP1000_IDE_SIZE 0x00100000 /* actually it's only 0x1000 */
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#define IRQ_HARDDISK IRQ_EINT2
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/*
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* IDE registers definition
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*/
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#define IDE_CONTROL_BASE (MP1000_IDE_BASE + 0x1000)
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#define IDE_BASE_OFF (MP1000_IDE_BASE)
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#define IDE_WRITE_DEVICE_DATA (IDE_BASE_OFF + 0x0)
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#define IDE_FEATURES_REGISTER (IDE_BASE_OFF + 0x2)
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#define IDE_SECTOR_COUNT_REGISTER (IDE_BASE_OFF + 0x4)
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#define IDE_SECTOR_NUMBER_REGISTER (IDE_BASE_OFF + 0x6)
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#define IDE_CYLINDER_LOW_REGISTER (IDE_BASE_OFF + 0x8)
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#define IDE_CYLINDER_HIGH_REGISTER (IDE_BASE_OFF + 0xa)
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#define IDE_DEVICE_HEAD_REGISTER (IDE_BASE_OFF + 0xc)
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#define IDE_COMMAND_DATA_REGISTER (IDE_BASE_OFF + 0xe)
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#define IDE_DEVICE_CONTROL_REGISTER (IDE_CONTROL_BASE + 0xc)
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#define IDE_IRQ IRQ_EINT2
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#define RTC_PORT(x) (MP1000_LIO_BASE+0x2000 + (x*2))
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#define RTC_ALWAYS_BCD 0
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/*
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// Definitions of the bit fields in the HwPortA register for the
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// MP1000 board.
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*/
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#define HwPortAKeyboardRow1 0x00000001
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#define HwPortAKeyboardRow2 0x00000002
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#define HwPortAKeyboardRow3 0x00000004
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#define HwPortAKeyboardRow4 0x00000008
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#define HwPortAKeyboardRow5 0x00000010
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#define HwPortAKeyboardRow6 0x00000020
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#define HwPortALCDEnable 0x00000040
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#define HwPortAOffhook 0x00000080
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/*
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// Definitions of the bit fields in the HwPortB register for the
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// MP1000 board.
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*/
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#define HwPortBL3Mode 0x00000001
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#define HwPortBL3Clk 0x00000002
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#define HwPortBSClk 0x00000001
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#define HwPortBSData 0x00000002
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#define HwPortBL3Data 0x00000004
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#define HwPortBMute 0x00000008
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#define HwPortBQD0 0x00000010
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#define HwPortBQD1 0x00000020
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#define HwPortBQD2 0x00000040
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#define HwPortBQD3 0x00000080
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/*
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// Definitions of the bit fields in the HwPortD register for the
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// MP1000 board.
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*/
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#define HwPortDLED1 0x00000001
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#define HwPortDLED2 0x00000002
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#define HwPortDLED3 0x00000004
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#define HwPortDLED4 0x00000008
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#define HwPortDLED5 0x00000010
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#define HwPortDEECS 0x00000020
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#define HwPortBRTS 0x00000040
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#define HwPortBRI 0x00000080
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/*
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// Definitions of the bit fields in the HwPortE register for the
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// MP1000 board.
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*/
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#define HwPortECLE 0x00000001
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#define HwPortESepromDOut 0x00000001
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#define HwPortEALE 0x00000002
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#define HwPortESepromDIn 0x00000002
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#define HwPortENANDCS 0x00000004
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#define HwPortESepromCLK 0x00000004
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#endif // #if defined (CONFIG_MACH_MP1000)
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#endif
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