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332 lines
10 KiB
332 lines
10 KiB
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV Broadcast Assist Unit definitions
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*
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* Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_X86_UV_UV_BAU_H
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#define _ASM_X86_UV_UV_BAU_H
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#include <linux/bitmap.h>
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#define BITSPERBYTE 8
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/*
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* Broadcast Assist Unit messaging structures
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*
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* Selective Broadcast activations are induced by software action
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* specifying a particular 8-descriptor "set" via a 6-bit index written
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* to an MMR.
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* Thus there are 64 unique 512-byte sets of SB descriptors - one set for
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* each 6-bit index value. These descriptor sets are mapped in sequence
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* starting with set 0 located at the address specified in the
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* BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
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* set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
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*
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* We will use 31 sets, one for sending BAU messages from each of the 32
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* cpu's on the node.
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*
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* TLB shootdown will use the first of the 8 descriptors of each set.
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* Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
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*/
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#define UV_ITEMS_PER_DESCRIPTOR 8
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#define UV_CPUS_PER_ACT_STATUS 32
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#define UV_ACT_STATUS_MASK 0x3
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#define UV_ACT_STATUS_SIZE 2
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#define UV_ACTIVATION_DESCRIPTOR_SIZE 32
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#define UV_DISTRIBUTION_SIZE 256
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#define UV_SW_ACK_NPENDING 8
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#define UV_NET_ENDPOINT_INTD 0x38
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#define UV_DESC_BASE_PNODE_SHIFT 49
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#define UV_PAYLOADQ_PNODE_SHIFT 49
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#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
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#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
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/*
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* bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
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*/
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#define DESC_STATUS_IDLE 0
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#define DESC_STATUS_ACTIVE 1
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#define DESC_STATUS_DESTINATION_TIMEOUT 2
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#define DESC_STATUS_SOURCE_TIMEOUT 3
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/*
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* source side threshholds at which message retries print a warning
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*/
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#define SOURCE_TIMEOUT_LIMIT 20
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#define DESTINATION_TIMEOUT_LIMIT 20
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/*
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* number of entries in the destination side payload queue
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*/
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#define DEST_Q_SIZE 17
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/*
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* number of destination side software ack resources
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*/
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#define DEST_NUM_RESOURCES 8
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#define MAX_CPUS_PER_NODE 32
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/*
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* completion statuses for sending a TLB flush message
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*/
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#define FLUSH_RETRY 1
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#define FLUSH_GIVEUP 2
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#define FLUSH_COMPLETE 3
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/*
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* Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
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* If the 'multilevel' flag in the header portion of the descriptor
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* has been set to 0, then endpoint multi-unicast mode is selected.
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* The distribution specification (32 bytes) is interpreted as a 256-bit
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* distribution vector. Adjacent bits correspond to consecutive even numbered
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* nodeIDs. The result of adding the index of a given bit to the 15-bit
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* 'base_dest_nodeid' field of the header corresponds to the
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* destination nodeID associated with that specified bit.
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*/
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struct bau_target_nodemask {
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unsigned long bits[BITS_TO_LONGS(256)];
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};
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/*
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* mask of cpu's on a node
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* (during initialization we need to check that unsigned long has
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* enough bits for max. cpu's per node)
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*/
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struct bau_local_cpumask {
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unsigned long bits;
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};
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/*
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* Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
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* only 12 bytes (96 bits) of the payload area are usable.
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* An additional 3 bytes (bits 27:4) of the header address are carried
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* to the next bytes of the destination payload queue.
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* And an additional 2 bytes of the header Suppl_A field are also
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* carried to the destination payload queue.
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* But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
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* of the destination payload queue, which is written by the hardware
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* with the s/w ack resource bit vector.
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* [ effective message contents (16 bytes (128 bits) maximum), not counting
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* the s/w ack bit vector ]
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*/
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/*
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* The payload is software-defined for INTD transactions
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*/
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struct bau_msg_payload {
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unsigned long address; /* signifies a page or all TLB's
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of the cpu */
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/* 64 bits */
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unsigned short sending_cpu; /* filled in by sender */
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/* 16 bits */
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unsigned short acknowledge_count;/* filled in by destination */
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/* 16 bits */
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unsigned int reserved1:32; /* not usable */
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};
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/*
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* Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
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* see table 4.2.3.0.1 in broacast_assist spec.
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*/
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struct bau_msg_header {
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int dest_subnodeid:6; /* must be zero */
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/* bits 5:0 */
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int base_dest_nodeid:15; /* nasid>>1 (pnode) of first bit in node_map */
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/* bits 20:6 */
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int command:8; /* message type */
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/* bits 28:21 */
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/* 0x38: SN3net EndPoint Message */
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int rsvd_1:3; /* must be zero */
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/* bits 31:29 */
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/* int will align on 32 bits */
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int rsvd_2:9; /* must be zero */
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/* bits 40:32 */
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/* Suppl_A is 56-41 */
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int payload_2a:8; /* becomes byte 16 of msg */
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/* bits 48:41 */ /* not currently using */
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int payload_2b:8; /* becomes byte 17 of msg */
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/* bits 56:49 */ /* not currently using */
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/* Address field (96:57) is never used as an
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address (these are address bits 42:3) */
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int rsvd_3:1; /* must be zero */
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/* bit 57 */
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/* address bits 27:4 are payload */
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/* these 24 bits become bytes 12-14 of msg */
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int replied_to:1; /* sent as 0 by the source to byte 12 */
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/* bit 58 */
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int payload_1a:5; /* not currently used */
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/* bits 63:59 */
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int payload_1b:8; /* not currently used */
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/* bits 71:64 */
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int payload_1c:8; /* not currently used */
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/* bits 79:72 */
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int payload_1d:2; /* not currently used */
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/* bits 81:80 */
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int rsvd_4:7; /* must be zero */
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/* bits 88:82 */
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int sw_ack_flag:1; /* software acknowledge flag */
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/* bit 89 */
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/* INTD trasactions at destination are to
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wait for software acknowledge */
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int rsvd_5:6; /* must be zero */
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/* bits 95:90 */
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int rsvd_6:5; /* must be zero */
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/* bits 100:96 */
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int int_both:1; /* if 1, interrupt both sockets on the blade */
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/* bit 101*/
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int fairness:3; /* usually zero */
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/* bits 104:102 */
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int multilevel:1; /* multi-level multicast format */
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/* bit 105 */
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/* 0 for TLB: endpoint multi-unicast messages */
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int chaining:1; /* next descriptor is part of this activation*/
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/* bit 106 */
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int rsvd_7:21; /* must be zero */
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/* bits 127:107 */
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};
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/*
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* The activation descriptor:
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* The format of the message to send, plus all accompanying control
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* Should be 64 bytes
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*/
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struct bau_desc {
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struct bau_target_nodemask distribution;
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/*
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* message template, consisting of header and payload:
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*/
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struct bau_msg_header header;
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struct bau_msg_payload payload;
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};
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/*
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* -payload-- ---------header------
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* bytes 0-11 bits 41-56 bits 58-81
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* A B (2) C (3)
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*
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* A/B/C are moved to:
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* A C B
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* bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
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* ------------payload queue-----------
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*/
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/*
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* The payload queue on the destination side is an array of these.
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* With BAU_MISC_CONTROL set for software acknowledge mode, the messages
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* are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
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* bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
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* (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
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* sw_ack_vector and payload_2)
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* "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
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* Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
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* operation."
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*/
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struct bau_payload_queue_entry {
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unsigned long address; /* signifies a page or all TLB's
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of the cpu */
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/* 64 bits, bytes 0-7 */
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unsigned short sending_cpu; /* cpu that sent the message */
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/* 16 bits, bytes 8-9 */
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unsigned short acknowledge_count; /* filled in by destination */
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/* 16 bits, bytes 10-11 */
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unsigned short replied_to:1; /* sent as 0 by the source */
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/* 1 bit */
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unsigned short unused1:7; /* not currently using */
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/* 7 bits: byte 12) */
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unsigned char unused2[2]; /* not currently using */
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/* bytes 13-14 */
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unsigned char sw_ack_vector; /* filled in by the hardware */
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/* byte 15 (bits 127:120) */
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unsigned char unused4[3]; /* not currently using bytes 17-19 */
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/* bytes 17-19 */
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int number_of_cpus; /* filled in at destination */
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/* 32 bits, bytes 20-23 (aligned) */
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unsigned char unused5[8]; /* not using */
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/* bytes 24-31 */
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};
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/*
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* one for every slot in the destination payload queue
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*/
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struct bau_msg_status {
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struct bau_local_cpumask seen_by; /* map of cpu's */
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};
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/*
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* one for every slot in the destination software ack resources
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*/
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struct bau_sw_ack_status {
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struct bau_payload_queue_entry *msg; /* associated message */
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int watcher; /* cpu monitoring, or -1 */
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};
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/*
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* one on every node and per-cpu; to locate the software tables
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*/
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struct bau_control {
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struct bau_desc *descriptor_base;
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struct bau_payload_queue_entry *bau_msg_head;
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struct bau_payload_queue_entry *va_queue_first;
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struct bau_payload_queue_entry *va_queue_last;
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struct bau_msg_status *msg_statuses;
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int *watching; /* pointer to array */
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};
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/*
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* This structure is allocated per_cpu for UV TLB shootdown statistics.
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*/
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struct ptc_stats {
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unsigned long ptc_i; /* number of IPI-style flushes */
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unsigned long requestor; /* number of nodes this cpu sent to */
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unsigned long requestee; /* times cpu was remotely requested */
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unsigned long alltlb; /* times all tlb's on this cpu were flushed */
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unsigned long onetlb; /* times just one tlb on this cpu was flushed */
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unsigned long s_retry; /* retries on source side timeouts */
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unsigned long d_retry; /* retries on destination side timeouts */
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unsigned long sflush; /* cycles spent in uv_flush_tlb_others */
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unsigned long dflush; /* cycles spent on destination side */
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unsigned long retriesok; /* successes on retries */
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unsigned long nomsg; /* interrupts with no message */
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unsigned long multmsg; /* interrupts with multiple messages */
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unsigned long ntargeted;/* nodes targeted */
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};
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static inline int bau_node_isset(int node, struct bau_target_nodemask *dstp)
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{
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return constant_test_bit(node, &dstp->bits[0]);
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}
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static inline void bau_node_set(int node, struct bau_target_nodemask *dstp)
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{
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__set_bit(node, &dstp->bits[0]);
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}
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static inline void bau_nodes_clear(struct bau_target_nodemask *dstp, int nbits)
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{
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bitmap_zero(&dstp->bits[0], nbits);
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}
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static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
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{
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bitmap_zero(&dstp->bits, nbits);
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}
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#define cpubit_isset(cpu, bau_local_cpumask) \
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test_bit((cpu), (bau_local_cpumask).bits)
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extern int uv_flush_tlb_others(cpumask_t *, struct mm_struct *, unsigned long);
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extern void uv_bau_message_intr1(void);
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extern void uv_bau_timeout_intr1(void);
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#endif /* _ASM_X86_UV_UV_BAU_H */
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