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115 lines
4.3 KiB
115 lines
4.3 KiB
/*
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* arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
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*
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* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* WM8505 Interrupt Sources */
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#define IRQ_UHCI 0 /* UHC FS (UHCI?) */
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#define IRQ_EHCI 1 /* UHC HS */
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#define IRQ_UDCDMA 2 /* UDC DMA */
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/* Reserved */
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#define IRQ_PS2MOUSE 4 /* PS/2 Mouse */
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#define IRQ_UDC 5 /* UDC */
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#define IRQ_EXT0 6 /* External Interrupt 0 */
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#define IRQ_EXT1 7 /* External Interrupt 1 */
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#define IRQ_KEYPAD 8 /* Keypad */
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#define IRQ_DMA 9 /* DMA Controller */
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#define IRQ_ETHER 10 /* Ethernet MAC */
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/* Reserved */
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/* Reserved */
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#define IRQ_EXT2 13 /* External Interrupt 2 */
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#define IRQ_EXT3 14 /* External Interrupt 3 */
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#define IRQ_EXT4 15 /* External Interrupt 4 */
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#define IRQ_APB 16 /* APB Bridge */
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#define IRQ_DMA0 17 /* DMA Channel 0 */
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#define IRQ_I2C1 18 /* I2C 1 */
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#define IRQ_I2C0 19 /* I2C 0 */
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#define IRQ_SDMMC 20 /* SD/MMC Controller */
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#define IRQ_SDMMC_DMA 21 /* SD/MMC Controller DMA */
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#define IRQ_PMC_WU 22 /* Power Management Controller Wakeup */
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#define IRQ_PS2KBD 23 /* PS/2 Keyboard */
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#define IRQ_SPI0 24 /* SPI 0 */
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#define IRQ_SPI1 25 /* SPI 1 */
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#define IRQ_SPI2 26 /* SPI 2 */
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#define IRQ_DMA1 27 /* DMA Channel 1 */
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#define IRQ_NAND 28 /* NAND Flash Controller */
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#define IRQ_NAND_DMA 29 /* NAND Flash Controller DMA */
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#define IRQ_UART5 30 /* UART 5 */
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#define IRQ_UART4 31 /* UART 4 */
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#define IRQ_UART0 32 /* UART 0 */
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#define IRQ_UART1 33 /* UART 1 */
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#define IRQ_DMA2 34 /* DMA Channel 2 */
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#define IRQ_I2S 35 /* I2S */
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#define IRQ_PMCOS0 36 /* PMC OS Timer 0 */
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#define IRQ_PMCOS1 37 /* PMC OS Timer 1 */
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#define IRQ_PMCOS2 38 /* PMC OS Timer 2 */
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#define IRQ_PMCOS3 39 /* PMC OS Timer 3 */
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#define IRQ_DMA3 40 /* DMA Channel 3 */
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#define IRQ_DMA4 41 /* DMA Channel 4 */
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#define IRQ_AC97 42 /* AC97 Interface */
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/* Reserved */
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#define IRQ_NOR 44 /* NOR Flash Controller */
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#define IRQ_DMA5 45 /* DMA Channel 5 */
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#define IRQ_DMA6 46 /* DMA Channel 6 */
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#define IRQ_UART2 47 /* UART 2 */
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#define IRQ_RTC 48 /* RTC Interrupt */
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#define IRQ_RTCSM 49 /* RTC Second/Minute Update Interrupt */
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#define IRQ_UART3 50 /* UART 3 */
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#define IRQ_DMA7 51 /* DMA Channel 7 */
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#define IRQ_EXT5 52 /* External Interrupt 5 */
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#define IRQ_EXT6 53 /* External Interrupt 6 */
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#define IRQ_EXT7 54 /* External Interrupt 7 */
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#define IRQ_CIR 55 /* CIR */
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#define IRQ_SIC0 56 /* SIC IRQ0 */
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#define IRQ_SIC1 57 /* SIC IRQ1 */
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#define IRQ_SIC2 58 /* SIC IRQ2 */
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#define IRQ_SIC3 59 /* SIC IRQ3 */
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#define IRQ_SIC4 60 /* SIC IRQ4 */
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#define IRQ_SIC5 61 /* SIC IRQ5 */
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#define IRQ_SIC6 62 /* SIC IRQ6 */
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#define IRQ_SIC7 63 /* SIC IRQ7 */
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/* Reserved */
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#define IRQ_JPEGDEC 65 /* JPEG Decoder */
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#define IRQ_SAE 66 /* SAE (?) */
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/* Reserved */
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#define IRQ_VPU 79 /* Video Processing Unit */
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#define IRQ_VPP 80 /* Video Post-Processor */
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#define IRQ_VID 81 /* Video Digital Input Interface */
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#define IRQ_SPU 82 /* SPU (?) */
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#define IRQ_PIP 83 /* PIP Error */
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#define IRQ_GE 84 /* Graphic Engine */
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#define IRQ_GOV 85 /* Graphic Overlay Engine */
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#define IRQ_DVO 86 /* Digital Video Output */
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/* Reserved */
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#define IRQ_DMA8 92 /* DMA Channel 8 */
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#define IRQ_DMA9 93 /* DMA Channel 9 */
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#define IRQ_DMA10 94 /* DMA Channel 10 */
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#define IRQ_DMA11 95 /* DMA Channel 11 */
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#define IRQ_DMA12 96 /* DMA Channel 12 */
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#define IRQ_DMA13 97 /* DMA Channel 13 */
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#define IRQ_DMA14 98 /* DMA Channel 14 */
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#define IRQ_DMA15 99 /* DMA Channel 15 */
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/* Reserved */
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#define IRQ_GOVW 111 /* GOVW (?) */
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#define IRQ_GOVRSDSCD 112 /* GOVR SDSCD (?) */
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#define IRQ_GOVRSDMIF 113 /* GOVR SDMIF (?) */
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#define IRQ_GOVRHDSCD 114 /* GOVR HDSCD (?) */
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#define IRQ_GOVRHDMIF 115 /* GOVR HDMIF (?) */
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#define WM8505_NR_IRQS 116
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