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400 lines
8.4 KiB
400 lines
8.4 KiB
/*
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* linux/arch/arm/mach-pxa/pxa3xx-ulpi.c
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*
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* code specific to pxa3xx aka Monahans
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*
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* Copyright (C) 2010 CompuLab Ltd.
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*
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* 2010-13-07: Igor Grinberg <grinberg@compulab.co.il>
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* initial version: pxa310 USB Host mode support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/usb.h>
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#include <linux/usb/otg.h>
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#include <mach/hardware.h>
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#include <mach/regs-u2d.h>
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#include <mach/pxa3xx-u2d.h>
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struct pxa3xx_u2d_ulpi {
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struct clk *clk;
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void __iomem *mmio_base;
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struct otg_transceiver *otg;
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unsigned int ulpi_mode;
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};
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static struct pxa3xx_u2d_ulpi *u2d;
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static inline u32 u2d_readl(u32 reg)
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{
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return __raw_readl(u2d->mmio_base + reg);
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}
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static inline void u2d_writel(u32 reg, u32 val)
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{
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__raw_writel(val, u2d->mmio_base + reg);
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}
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#if defined(CONFIG_PXA310_ULPI)
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enum u2d_ulpi_phy_mode {
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SYNCH = 0,
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CARKIT = (1 << 0),
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SER_3PIN = (1 << 1),
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SER_6PIN = (1 << 2),
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LOWPOWER = (1 << 3),
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};
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static inline enum u2d_ulpi_phy_mode pxa310_ulpi_get_phymode(void)
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{
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return (u2d_readl(U2DOTGUSR) >> 28) & 0xF;
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}
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static int pxa310_ulpi_poll(void)
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{
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int timeout = 50000;
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while (timeout--) {
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if (!(u2d_readl(U2DOTGUCR) & U2DOTGUCR_RUN))
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return 0;
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cpu_relax();
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}
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pr_warning("%s: ULPI access timed out!\n", __func__);
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return -ETIMEDOUT;
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}
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static int pxa310_ulpi_read(struct otg_transceiver *otg, u32 reg)
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{
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int err;
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if (pxa310_ulpi_get_phymode() != SYNCH) {
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pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
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return -EBUSY;
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}
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u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << 16));
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msleep(5);
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err = pxa310_ulpi_poll();
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if (err)
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return err;
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return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA;
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}
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static int pxa310_ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
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{
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if (pxa310_ulpi_get_phymode() != SYNCH) {
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pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
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return -EBUSY;
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}
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u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8));
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msleep(5);
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return pxa310_ulpi_poll();
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}
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struct otg_io_access_ops pxa310_ulpi_access_ops = {
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.read = pxa310_ulpi_read,
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.write = pxa310_ulpi_write,
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};
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static void pxa310_otg_transceiver_rtsm(void)
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{
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u32 u2dotgcr;
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/* put PHY to sync mode */
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u2dotgcr = u2d_readl(U2DOTGCR);
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u2dotgcr |= U2DOTGCR_RTSM | U2DOTGCR_UTMID;
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u2d_writel(U2DOTGCR, u2dotgcr);
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msleep(10);
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/* setup OTG sync mode */
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u2dotgcr = u2d_readl(U2DOTGCR);
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u2dotgcr |= U2DOTGCR_ULAF;
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u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
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u2d_writel(U2DOTGCR, u2dotgcr);
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}
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static int pxa310_start_otg_host_transcvr(struct usb_bus *host)
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{
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int err;
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pxa310_otg_transceiver_rtsm();
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err = otg_init(u2d->otg);
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if (err) {
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pr_err("OTG transceiver init failed");
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return err;
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}
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err = otg_set_vbus(u2d->otg, 1);
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if (err) {
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pr_err("OTG transceiver VBUS set failed");
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return err;
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}
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err = otg_set_host(u2d->otg, host);
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if (err)
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pr_err("OTG transceiver Host mode set failed");
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return err;
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}
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static int pxa310_start_otg_hc(struct usb_bus *host)
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{
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u32 u2dotgcr;
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int err;
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/* disable USB device controller */
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u2d_writel(U2DCR, u2d_readl(U2DCR) & ~U2DCR_UDE);
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u2d_writel(U2DOTGCR, u2d_readl(U2DOTGCR) | U2DOTGCR_UTMID);
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u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
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err = pxa310_start_otg_host_transcvr(host);
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if (err)
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return err;
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/* set xceiver mode */
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if (u2d->ulpi_mode & ULPI_IC_6PIN_SERIAL)
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u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) & ~U2DP3CR_P2SS);
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else if (u2d->ulpi_mode & ULPI_IC_3PIN_SERIAL)
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u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) | U2DP3CR_P2SS);
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/* start OTG host controller */
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u2dotgcr = u2d_readl(U2DOTGCR) | U2DOTGCR_SMAF;
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u2d_writel(U2DOTGCR, u2dotgcr & ~(U2DOTGCR_ULAF | U2DOTGCR_CKAF));
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return 0;
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}
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static void pxa310_stop_otg_hc(void)
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{
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pxa310_otg_transceiver_rtsm();
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otg_set_host(u2d->otg, NULL);
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otg_set_vbus(u2d->otg, 0);
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otg_shutdown(u2d->otg);
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}
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static void pxa310_u2d_setup_otg_hc(void)
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{
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u32 u2dotgcr;
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u2dotgcr = u2d_readl(U2DOTGCR);
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u2dotgcr |= U2DOTGCR_ULAF | U2DOTGCR_UTMID;
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u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
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u2d_writel(U2DOTGCR, u2dotgcr);
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msleep(5);
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u2d_writel(U2DOTGCR, u2dotgcr | U2DOTGCR_ULE);
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msleep(5);
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u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
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}
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static int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
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{
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unsigned int ulpi_mode = ULPI_OTG_DRVVBUS;
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if (pdata) {
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if (pdata->ulpi_mode & ULPI_SER_6PIN)
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ulpi_mode |= ULPI_IC_6PIN_SERIAL;
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else if (pdata->ulpi_mode & ULPI_SER_3PIN)
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ulpi_mode |= ULPI_IC_3PIN_SERIAL;
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}
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u2d->ulpi_mode = ulpi_mode;
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u2d->otg = otg_ulpi_create(&pxa310_ulpi_access_ops, ulpi_mode);
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if (!u2d->otg)
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return -ENOMEM;
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u2d->otg->io_priv = u2d->mmio_base;
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return 0;
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}
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static void pxa310_otg_exit(void)
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{
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kfree(u2d->otg);
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}
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#else
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static inline void pxa310_u2d_setup_otg_hc(void) {}
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static inline int pxa310_start_otg_hc(struct usb_bus *host)
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{
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return 0;
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}
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static inline void pxa310_stop_otg_hc(void) {}
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static inline int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
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{
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return 0;
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}
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static inline void pxa310_otg_exit(void) {}
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#endif /* CONFIG_PXA310_ULPI */
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int pxa3xx_u2d_start_hc(struct usb_bus *host)
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{
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int err = 0;
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/* In case the PXA3xx ULPI isn't used, do nothing. */
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if (!u2d)
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return 0;
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clk_enable(u2d->clk);
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if (cpu_is_pxa310()) {
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pxa310_u2d_setup_otg_hc();
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err = pxa310_start_otg_hc(host);
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}
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return err;
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}
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void pxa3xx_u2d_stop_hc(struct usb_bus *host)
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{
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/* In case the PXA3xx ULPI isn't used, do nothing. */
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if (!u2d)
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return;
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if (cpu_is_pxa310())
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pxa310_stop_otg_hc();
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clk_disable(u2d->clk);
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}
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static int pxa3xx_u2d_probe(struct platform_device *pdev)
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{
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struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
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struct resource *r;
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int err;
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u2d = kzalloc(sizeof(struct pxa3xx_u2d_ulpi), GFP_KERNEL);
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if (!u2d) {
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dev_err(&pdev->dev, "failed to allocate memory\n");
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return -ENOMEM;
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}
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u2d->clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(u2d->clk)) {
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dev_err(&pdev->dev, "failed to get u2d clock\n");
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err = PTR_ERR(u2d->clk);
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goto err_free_mem;
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}
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "no IO memory resource defined\n");
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err = -ENODEV;
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goto err_put_clk;
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}
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r = request_mem_region(r->start, resource_size(r), pdev->name);
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if (!r) {
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dev_err(&pdev->dev, "failed to request memory resource\n");
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err = -EBUSY;
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goto err_put_clk;
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}
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u2d->mmio_base = ioremap(r->start, resource_size(r));
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if (!u2d->mmio_base) {
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dev_err(&pdev->dev, "ioremap() failed\n");
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err = -ENODEV;
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goto err_free_res;
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}
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if (pdata->init) {
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err = pdata->init(&pdev->dev);
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if (err)
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goto err_free_io;
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}
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/* Only PXA310 U2D has OTG functionality */
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if (cpu_is_pxa310()) {
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err = pxa310_otg_init(pdata);
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if (err)
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goto err_free_plat;
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}
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platform_set_drvdata(pdev, &u2d);
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return 0;
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err_free_plat:
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if (pdata->exit)
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pdata->exit(&pdev->dev);
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err_free_io:
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iounmap(u2d->mmio_base);
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err_free_res:
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release_mem_region(r->start, resource_size(r));
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err_put_clk:
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clk_put(u2d->clk);
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err_free_mem:
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kfree(u2d);
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return err;
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}
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static int pxa3xx_u2d_remove(struct platform_device *pdev)
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{
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struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
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struct resource *r;
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if (cpu_is_pxa310()) {
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pxa310_stop_otg_hc();
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pxa310_otg_exit();
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}
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if (pdata->exit)
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pdata->exit(&pdev->dev);
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platform_set_drvdata(pdev, NULL);
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iounmap(u2d->mmio_base);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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release_mem_region(r->start, resource_size(r));
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clk_put(u2d->clk);
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kfree(u2d);
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return 0;
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}
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static struct platform_driver pxa3xx_u2d_ulpi_driver = {
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.driver = {
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.name = "pxa3xx-u2d",
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.owner = THIS_MODULE,
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},
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.probe = pxa3xx_u2d_probe,
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.remove = pxa3xx_u2d_remove,
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};
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static int pxa3xx_u2d_ulpi_init(void)
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{
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return platform_driver_register(&pxa3xx_u2d_ulpi_driver);
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}
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module_init(pxa3xx_u2d_ulpi_init);
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static void __exit pxa3xx_u2d_ulpi_exit(void)
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{
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platform_driver_unregister(&pxa3xx_u2d_ulpi_driver);
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}
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module_exit(pxa3xx_u2d_ulpi_exit);
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MODULE_DESCRIPTION("PXA3xx U2D ULPI driver");
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MODULE_AUTHOR("Igor Grinberg");
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MODULE_LICENSE("GPL v2");
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