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88 lines
3.4 KiB
88 lines
3.4 KiB
/*
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* arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
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*
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* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* VT8500 Interrupt Sources */
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#define IRQ_JPEGENC 0 /* JPEG Encoder */
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#define IRQ_JPEGDEC 1 /* JPEG Decoder */
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/* Reserved */
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#define IRQ_PATA 3 /* PATA Controller */
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/* Reserved */
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#define IRQ_DMA 5 /* DMA Controller */
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#define IRQ_EXT0 6 /* External Interrupt 0 */
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#define IRQ_EXT1 7 /* External Interrupt 1 */
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#define IRQ_GE 8 /* Graphic Engine */
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#define IRQ_GOV 9 /* Graphic Overlay Engine */
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#define IRQ_ETHER 10 /* Ethernet MAC */
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#define IRQ_MPEGTS 11 /* Transport Stream Interface */
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#define IRQ_LCDC 12 /* LCD Controller */
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#define IRQ_EXT2 13 /* External Interrupt 2 */
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#define IRQ_EXT3 14 /* External Interrupt 3 */
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#define IRQ_EXT4 15 /* External Interrupt 4 */
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#define IRQ_CIPHER 16 /* Cipher */
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#define IRQ_VPP 17 /* Video Post-Processor */
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#define IRQ_I2C1 18 /* I2C 1 */
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#define IRQ_I2C0 19 /* I2C 0 */
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#define IRQ_SDMMC 20 /* SD/MMC Controller */
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#define IRQ_SDMMC_DMA 21 /* SD/MMC Controller DMA */
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#define IRQ_PMC_WU 22 /* Power Management Controller Wakeup */
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/* Reserved */
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#define IRQ_SPI0 24 /* SPI 0 */
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#define IRQ_SPI1 25 /* SPI 1 */
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#define IRQ_SPI2 26 /* SPI 2 */
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#define IRQ_LCDDF 27 /* LCD Data Formatter */
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#define IRQ_NAND 28 /* NAND Flash Controller */
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#define IRQ_NAND_DMA 29 /* NAND Flash Controller DMA */
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#define IRQ_MS 30 /* MemoryStick Controller */
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#define IRQ_MS_DMA 31 /* MemoryStick Controller DMA */
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#define IRQ_UART0 32 /* UART 0 */
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#define IRQ_UART1 33 /* UART 1 */
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#define IRQ_I2S 34 /* I2S */
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#define IRQ_PCM 35 /* PCM */
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#define IRQ_PMCOS0 36 /* PMC OS Timer 0 */
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#define IRQ_PMCOS1 37 /* PMC OS Timer 1 */
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#define IRQ_PMCOS2 38 /* PMC OS Timer 2 */
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#define IRQ_PMCOS3 39 /* PMC OS Timer 3 */
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#define IRQ_VPU 40 /* Video Processing Unit */
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#define IRQ_VID 41 /* Video Digital Input Interface */
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#define IRQ_AC97 42 /* AC97 Interface */
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#define IRQ_EHCI 43 /* USB */
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#define IRQ_NOR 44 /* NOR Flash Controller */
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#define IRQ_PS2MOUSE 45 /* PS/2 Mouse */
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#define IRQ_PS2KBD 46 /* PS/2 Keyboard */
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#define IRQ_UART2 47 /* UART 2 */
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#define IRQ_RTC 48 /* RTC Interrupt */
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#define IRQ_RTCSM 49 /* RTC Second/Minute Update Interrupt */
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#define IRQ_UART3 50 /* UART 3 */
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#define IRQ_ADC 51 /* ADC */
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#define IRQ_EXT5 52 /* External Interrupt 5 */
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#define IRQ_EXT6 53 /* External Interrupt 6 */
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#define IRQ_EXT7 54 /* External Interrupt 7 */
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#define IRQ_CIR 55 /* CIR */
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#define IRQ_DMA0 56 /* DMA Channel 0 */
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#define IRQ_DMA1 57 /* DMA Channel 1 */
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#define IRQ_DMA2 58 /* DMA Channel 2 */
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#define IRQ_DMA3 59 /* DMA Channel 3 */
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#define IRQ_DMA4 60 /* DMA Channel 4 */
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#define IRQ_DMA5 61 /* DMA Channel 5 */
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#define IRQ_DMA6 62 /* DMA Channel 6 */
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#define IRQ_DMA7 63 /* DMA Channel 7 */
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#define VT8500_NR_IRQS 64
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