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121 lines
6.0 KiB
121 lines
6.0 KiB
/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <dt-bindings/clock/qcom,gcc-sdmshrike.h>
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#include "virtio_clk_common.h"
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static const char * const sa8195p_gcc_virtio_clocks[] = {
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[GCC_QUPV3_WRAP0_S0_CLK] = "gcc_qupv3_wrap0_s0_clk",
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[GCC_QUPV3_WRAP0_S1_CLK] = "gcc_qupv3_wrap0_s1_clk",
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[GCC_QUPV3_WRAP0_S2_CLK] = "gcc_qupv3_wrap0_s2_clk",
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[GCC_QUPV3_WRAP0_S3_CLK] = "gcc_qupv3_wrap0_s3_clk",
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[GCC_QUPV3_WRAP0_S4_CLK] = "gcc_qupv3_wrap0_s4_clk",
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[GCC_QUPV3_WRAP0_S5_CLK] = "gcc_qupv3_wrap0_s5_clk",
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[GCC_QUPV3_WRAP0_S6_CLK] = "gcc_qupv3_wrap0_s6_clk",
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[GCC_QUPV3_WRAP0_S7_CLK] = "gcc_qupv3_wrap0_s7_clk",
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[GCC_QUPV3_WRAP1_S0_CLK] = "gcc_qupv3_wrap1_s0_clk",
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[GCC_QUPV3_WRAP1_S1_CLK] = "gcc_qupv3_wrap1_s1_clk",
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[GCC_QUPV3_WRAP1_S2_CLK] = "gcc_qupv3_wrap1_s2_clk",
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[GCC_QUPV3_WRAP1_S3_CLK] = "gcc_qupv3_wrap1_s3_clk",
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[GCC_QUPV3_WRAP1_S4_CLK] = "gcc_qupv3_wrap1_s4_clk",
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[GCC_QUPV3_WRAP1_S5_CLK] = "gcc_qupv3_wrap1_s5_clk",
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[GCC_QUPV3_WRAP2_S0_CLK] = "gcc_qupv3_wrap2_s0_clk",
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[GCC_QUPV3_WRAP2_S1_CLK] = "gcc_qupv3_wrap2_s1_clk",
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[GCC_QUPV3_WRAP2_S2_CLK] = "gcc_qupv3_wrap2_s2_clk",
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[GCC_QUPV3_WRAP2_S3_CLK] = "gcc_qupv3_wrap2_s3_clk",
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[GCC_QUPV3_WRAP2_S4_CLK] = "gcc_qupv3_wrap2_s4_clk",
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[GCC_QUPV3_WRAP2_S5_CLK] = "gcc_qupv3_wrap2_s5_clk",
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[GCC_QUPV3_WRAP_0_M_AHB_CLK] = "gcc_qupv3_wrap_0_m_ahb_clk",
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[GCC_QUPV3_WRAP_0_S_AHB_CLK] = "gcc_qupv3_wrap_0_s_ahb_clk",
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[GCC_QUPV3_WRAP_1_M_AHB_CLK] = "gcc_qupv3_wrap_1_m_ahb_clk",
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[GCC_QUPV3_WRAP_1_S_AHB_CLK] = "gcc_qupv3_wrap_1_s_ahb_clk",
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[GCC_QUPV3_WRAP_2_M_AHB_CLK] = "gcc_qupv3_wrap_2_m_ahb_clk",
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[GCC_QUPV3_WRAP_2_S_AHB_CLK] = "gcc_qupv3_wrap_2_s_ahb_clk",
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[GCC_USB30_PRIM_MASTER_CLK] = "gcc_usb30_prim_master_clk",
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[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = "gcc_cfg_noc_usb3_prim_axi_clk",
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[GCC_AGGRE_USB3_PRIM_AXI_CLK] = "gcc_aggre_usb3_prim_axi_clk",
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[GCC_USB30_PRIM_MOCK_UTMI_CLK] = "gcc_usb30_prim_mock_utmi_clk",
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[GCC_USB30_PRIM_SLEEP_CLK] = "gcc_usb30_prim_sleep_clk",
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[GCC_USB3_PRIM_PHY_AUX_CLK] = "gcc_usb3_prim_phy_aux_clk",
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[GCC_USB3_PRIM_PHY_PIPE_CLK] = "gcc_usb3_prim_phy_pipe_clk",
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[GCC_USB3_PRIM_CLKREF_CLK] = "gcc_usb3_prim_clkref_en",
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[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = "gcc_usb3_prim_phy_com_aux_clk",
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[GCC_USB30_SEC_MASTER_CLK] = "gcc_usb30_sec_master_clk",
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[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = "gcc_cfg_noc_usb3_sec_axi_clk",
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[GCC_AGGRE_USB3_SEC_AXI_CLK] = "gcc_aggre_usb3_sec_axi_clk",
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[GCC_USB30_SEC_MOCK_UTMI_CLK] = "gcc_usb30_sec_mock_utmi_clk",
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[GCC_USB30_SEC_SLEEP_CLK] = "gcc_usb30_sec_sleep_clk",
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[GCC_USB3_SEC_PHY_AUX_CLK] = "gcc_usb3_sec_phy_aux_clk",
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[GCC_USB3_SEC_PHY_PIPE_CLK] = "gcc_usb3_sec_phy_pipe_clk",
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[GCC_USB3_SEC_CLKREF_CLK] = "gcc_usb3_sec_clkref_en",
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[GCC_USB3_SEC_PHY_COM_AUX_CLK] = "gcc_usb3_sec_phy_com_aux_clk",
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[GCC_PCIE_0_PIPE_CLK] = "gcc_pcie_0_pipe_clk",
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[GCC_PCIE_0_AUX_CLK] = "gcc_pcie_0_aux_clk",
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[GCC_PCIE_0_CFG_AHB_CLK] = "gcc_pcie_0_cfg_ahb_clk",
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[GCC_PCIE_0_MSTR_AXI_CLK] = "gcc_pcie_0_mstr_axi_clk",
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[GCC_PCIE_0_SLV_AXI_CLK] = "gcc_pcie_0_slv_axi_clk",
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[GCC_PCIE_0_CLKREF_CLK] = "gcc_pcie_0_clkref_en",
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[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = "gcc_pcie_0_slv_q2a_axi_clk",
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[GCC_PCIE_1_PIPE_CLK] = "gcc_pcie_1_pipe_clk",
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[GCC_PCIE_1_AUX_CLK] = "gcc_pcie_1_aux_clk",
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[GCC_PCIE_1_CFG_AHB_CLK] = "gcc_pcie_1_cfg_ahb_clk",
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[GCC_PCIE_1_MSTR_AXI_CLK] = "gcc_pcie_1_mstr_axi_clk",
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[GCC_PCIE_1_SLV_AXI_CLK] = "gcc_pcie_1_slv_axi_clk",
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[GCC_PCIE_1_CLKREF_CLK] = "gcc_pcie_1_clkref_en",
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[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = "gcc_pcie_1_slv_q2a_axi_clk",
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[GCC_PCIE_2_PIPE_CLK] = "gcc_pcie_2_pipe_clk",
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[GCC_PCIE_2_AUX_CLK] = "gcc_pcie_2_aux_clk",
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[GCC_PCIE_2_CFG_AHB_CLK] = "gcc_pcie_2_cfg_ahb_clk",
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[GCC_PCIE_2_MSTR_AXI_CLK] = "gcc_pcie_2_mstr_axi_clk",
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[GCC_PCIE_2_SLV_AXI_CLK] = "gcc_pcie_2_slv_axi_clk",
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[GCC_PCIE_2_CLKREF_CLK] = "gcc_pcie_2_clkref_en",
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[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = "gcc_pcie_2_slv_q2a_axi_clk",
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[GCC_PCIE_3_PIPE_CLK] = "gcc_pcie_3_pipe_clk",
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[GCC_PCIE_3_AUX_CLK] = "gcc_pcie_3_aux_clk",
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[GCC_PCIE_3_CFG_AHB_CLK] = "gcc_pcie_3_cfg_ahb_clk",
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[GCC_PCIE_3_MSTR_AXI_CLK] = "gcc_pcie_3_mstr_axi_clk",
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[GCC_PCIE_3_SLV_AXI_CLK] = "gcc_pcie_3_slv_axi_clk",
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[GCC_PCIE_3_CLKREF_CLK] = "gcc_pcie_3_clkref_en",
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[GCC_PCIE_3_SLV_Q2A_AXI_CLK] = "gcc_pcie_3_slv_q2a_axi_clk",
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[GCC_AGGRE_NOC_PCIE_TBU_CLK] = "gcc_aggre_noc_pcie_tbu_clk",
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[GCC_PCIE0_PHY_REFGEN_CLK] = "gcc_pcie0_phy_refgen_clk",
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[GCC_PCIE1_PHY_REFGEN_CLK] = "gcc_pcie1_phy_refgen_clk",
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[GCC_PCIE2_PHY_REFGEN_CLK] = "gcc_pcie2_phy_refgen_clk",
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[GCC_PCIE3_PHY_REFGEN_CLK] = "gcc_pcie3_phy_refgen_clk",
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[GCC_PCIE_PHY_AUX_CLK] = "gcc_pcie_phy_aux_clk",
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[GCC_SDCC2_AHB_CLK] = "gcc_sdcc2_ahb_clk",
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[GCC_SDCC2_APPS_CLK] = "gcc_sdcc2_apps_clk",
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[GCC_PRNG_AHB_CLK] = "gcc_prng_ahb_clk",
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};
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static const char * const sa8195p_gcc_virtio_resets[] = {
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[GCC_QUSB2PHY_PRIM_BCR] = "gcc_qusb2phy_prim_bcr",
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[GCC_QUSB2PHY_SEC_BCR] = "gcc_qusb2phy_sec_bcr",
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[GCC_USB30_PRIM_BCR] = "gcc_usb30_prim_master_clk",
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[GCC_USB30_SEC_BCR] = "gcc_usb30_sec_master_clk",
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[GCC_PCIE_0_BCR] = "gcc_pcie_0_mstr_axi_clk",
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[GCC_PCIE_0_PHY_BCR] = "gcc_pcie_0_phy_bcr",
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[GCC_PCIE_1_BCR] = "gcc_pcie_1_mstr_axi_clk",
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[GCC_PCIE_1_PHY_BCR] = "gcc_pcie_1_phy_bcr",
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[GCC_PCIE_2_BCR] = "gcc_pcie_2_mstr_axi_clk",
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[GCC_PCIE_2_PHY_BCR] = "gcc_pcie_2_phy_bcr",
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[GCC_PCIE_3_BCR] = "gcc_pcie_3_mstr_axi_clk",
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[GCC_PCIE_3_PHY_BCR] = "gcc_pcie_3_phy_bcr",
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};
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const struct clk_virtio_desc clk_virtio_sa8195p_gcc = {
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.clk_names = sa8195p_gcc_virtio_clocks,
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.num_clks = ARRAY_SIZE(sa8195p_gcc_virtio_clocks),
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.reset_names = sa8195p_gcc_virtio_resets,
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.num_resets = ARRAY_SIZE(sa8195p_gcc_virtio_resets),
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};
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