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556 lines
14 KiB
556 lines
14 KiB
/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "clk: %s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,scc-sm6150.h>
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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#include "clk-alpha-pll.h"
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#include "vdd-level-sm6150.h"
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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static DEFINE_VDD_REGULATORS(vdd_scc_cx, VDD_NUM, 1, vdd_corner);
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enum {
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P_AOSS_CC_RO_CLK,
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P_AON_SLEEP_CLK,
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P_CORE_PI_CXO_CLK,
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P_QDSP6SS_PLL_OUT_AUX,
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P_SCC_PLL_OUT_AUX,
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P_SCC_PLL_OUT_AUX2,
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P_SCC_PLL_OUT_EARLY,
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P_SSC_BI_PLL_TEST_SE,
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};
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static const struct parent_map scc_parent_map_0[] = {
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{ P_AOSS_CC_RO_CLK, 0 },
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{ P_AON_SLEEP_CLK, 1 },
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{ P_SCC_PLL_OUT_AUX2, 2 },
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{ P_CORE_PI_CXO_CLK, 3 },
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{ P_SCC_PLL_OUT_AUX, 4 },
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{ P_QDSP6SS_PLL_OUT_AUX, 5 },
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{ P_SCC_PLL_OUT_EARLY, 6 },
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{ P_SSC_BI_PLL_TEST_SE, 7 },
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};
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static const char * const scc_parent_names_0[] = {
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"bi_tcxo",
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"aon_sleep_clk",
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"scc_pll_out_aux2",
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"bi_tcxo",
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"scc_pll_out_aux",
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"qdsp6ss_pll_out_aux",
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"scc_pll",
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"ssc_bi_pll_test_se",
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};
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static const struct freq_tbl ftbl_scc_main_rcg_clk_src[] = {
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F(100000000, P_SCC_PLL_OUT_AUX, 2, 0, 0),
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F(200000000, P_SCC_PLL_OUT_AUX, 1, 0, 0),
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F(300000000, P_SCC_PLL_OUT_AUX2, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 scc_main_rcg_clk_src = {
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.cmd_rcgr = 0x1000,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = scc_parent_map_0,
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.freq_tbl = ftbl_scc_main_rcg_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "scc_main_rcg_clk_src",
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.parent_names = scc_parent_names_0,
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.num_parents = 8,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_scc_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 300000000,
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[VDD_LOW] = 600000000},
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},
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};
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static const struct freq_tbl ftbl_scc_qupv3_se0_clk_src[] = {
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F(7372800, P_SCC_PLL_OUT_AUX, 1, 576, 15625),
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F(14745600, P_SCC_PLL_OUT_AUX, 1, 1152, 15625),
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F(19200000, P_AOSS_CC_RO_CLK, 1, 0, 0),
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F(29491200, P_SCC_PLL_OUT_AUX, 1, 2304, 15625),
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F(32000000, P_SCC_PLL_OUT_AUX, 1, 4, 25),
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F(48000000, P_SCC_PLL_OUT_AUX, 1, 6, 25),
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F(64000000, P_SCC_PLL_OUT_AUX, 1, 8, 25),
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F(80000000, P_SCC_PLL_OUT_AUX, 1, 2, 5),
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F(96000000, P_SCC_PLL_OUT_AUX, 1, 12, 25),
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F(100000000, P_SCC_PLL_OUT_AUX, 2, 0, 0),
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F(102400000, P_SCC_PLL_OUT_AUX, 1, 64, 125),
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F(112000000, P_SCC_PLL_OUT_AUX, 1, 14, 25),
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F(117964800, P_SCC_PLL_OUT_AUX, 1, 9216, 15625),
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F(120000000, P_SCC_PLL_OUT_AUX, 1, 3, 5),
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F(128000000, P_SCC_PLL_OUT_AUX, 1, 16, 25),
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{ }
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};
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static struct clk_rcg2 scc_qupv3_se0_clk_src = {
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.cmd_rcgr = 0x2004,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = scc_parent_map_0,
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.freq_tbl = ftbl_scc_qupv3_se0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se0_clk_src",
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.parent_names = scc_parent_names_0,
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.num_parents = 8,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_scc_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 50000000,
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[VDD_LOWER] = 100000000,
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[VDD_LOW] = 150000000,
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[VDD_NOMINAL] = 200000000},
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},
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};
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static struct clk_rcg2 scc_qupv3_se1_clk_src = {
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.cmd_rcgr = 0x3004,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = scc_parent_map_0,
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.freq_tbl = ftbl_scc_qupv3_se0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se1_clk_src",
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.parent_names = scc_parent_names_0,
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.num_parents = 8,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_scc_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 50000000,
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[VDD_LOWER] = 100000000,
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[VDD_LOW] = 150000000,
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[VDD_NOMINAL] = 200000000},
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},
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};
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static struct clk_rcg2 scc_qupv3_se2_clk_src = {
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.cmd_rcgr = 0x4004,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = scc_parent_map_0,
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.freq_tbl = ftbl_scc_qupv3_se0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se2_clk_src",
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.parent_names = scc_parent_names_0,
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.num_parents = 8,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_scc_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 50000000,
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[VDD_LOWER] = 100000000,
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[VDD_LOW] = 150000000,
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[VDD_NOMINAL] = 200000000},
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},
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};
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static struct clk_rcg2 scc_qupv3_se3_clk_src = {
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.cmd_rcgr = 0xb004,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = scc_parent_map_0,
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.freq_tbl = ftbl_scc_qupv3_se0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se3_clk_src",
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.parent_names = scc_parent_names_0,
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.num_parents = 8,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_scc_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 50000000,
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[VDD_LOWER] = 100000000,
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[VDD_LOW] = 150000000,
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[VDD_NOMINAL] = 200000000},
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},
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};
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static struct clk_rcg2 scc_qupv3_se4_clk_src = {
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.cmd_rcgr = 0xc004,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = scc_parent_map_0,
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.freq_tbl = ftbl_scc_qupv3_se0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se4_clk_src",
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.parent_names = scc_parent_names_0,
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.num_parents = 8,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_scc_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 50000000,
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[VDD_LOWER] = 100000000,
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[VDD_LOW] = 150000000,
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[VDD_NOMINAL] = 200000000},
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},
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};
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static struct clk_rcg2 scc_qupv3_se5_clk_src = {
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.cmd_rcgr = 0xd004,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = scc_parent_map_0,
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.freq_tbl = ftbl_scc_qupv3_se0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se5_clk_src",
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.parent_names = scc_parent_names_0,
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.num_parents = 8,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_scc_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 50000000,
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[VDD_LOWER] = 100000000,
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[VDD_LOW] = 150000000,
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[VDD_NOMINAL] = 200000000},
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},
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};
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static struct clk_branch scc_qupv3_2xcore_clk = {
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.halt_reg = 0x5008,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x21000,
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.enable_mask = BIT(10),
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.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_2xcore_clk",
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.parent_names = (const char *[]){
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"scc_main_rcg_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch scc_qupv3_core_clk = {
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.halt_reg = 0x5010,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x21000,
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_core_clk",
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.parent_names = (const char *[]){
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"scc_main_rcg_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch scc_qupv3_m_hclk_clk = {
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.halt_reg = 0x9070,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x9064,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x21000,
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.enable_mask = BIT(1),
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.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_m_hclk_clk",
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.parent_names = (const char *[]){
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"scc_main_rcg_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch scc_qupv3_s_hclk_clk = {
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.halt_reg = 0x906c,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x9060,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x21000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_s_hclk_clk",
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.parent_names = (const char *[]){
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"scc_main_rcg_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch scc_qupv3_se0_clk = {
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.halt_reg = 0x2130,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x21000,
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.enable_mask = BIT(3),
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.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se0_clk",
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.parent_names = (const char *[]){
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"scc_qupv3_se0_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch scc_qupv3_se1_clk = {
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.halt_reg = 0x3130,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x21000,
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.enable_mask = BIT(4),
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.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se1_clk",
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.parent_names = (const char *[]){
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"scc_qupv3_se1_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch scc_qupv3_se2_clk = {
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.halt_reg = 0x4130,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x21000,
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.enable_mask = BIT(5),
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.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se2_clk",
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.parent_names = (const char *[]){
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"scc_qupv3_se2_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch scc_qupv3_se3_clk = {
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.halt_reg = 0xb130,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x21000,
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.enable_mask = BIT(6),
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.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se3_clk",
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.parent_names = (const char *[]){
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"scc_qupv3_se3_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch scc_qupv3_se4_clk = {
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.halt_reg = 0xc130,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x21000,
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.enable_mask = BIT(7),
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.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se4_clk",
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.parent_names = (const char *[]){
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"scc_qupv3_se4_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch scc_qupv3_se5_clk = {
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.halt_reg = 0xd130,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x21000,
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.enable_mask = BIT(8),
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.hw.init = &(struct clk_init_data){
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.name = "scc_qupv3_se5_clk",
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.parent_names = (const char *[]){
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"scc_qupv3_se5_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *scc_sm6150_clocks[] = {
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[SCC_MAIN_RCG_CLK_SRC] = &scc_main_rcg_clk_src.clkr,
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[SCC_QUPV3_2XCORE_CLK] = &scc_qupv3_2xcore_clk.clkr,
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[SCC_QUPV3_CORE_CLK] = &scc_qupv3_core_clk.clkr,
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[SCC_QUPV3_M_HCLK_CLK] = &scc_qupv3_m_hclk_clk.clkr,
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[SCC_QUPV3_S_HCLK_CLK] = &scc_qupv3_s_hclk_clk.clkr,
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[SCC_QUPV3_SE0_CLK] = &scc_qupv3_se0_clk.clkr,
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[SCC_QUPV3_SE0_CLK_SRC] = &scc_qupv3_se0_clk_src.clkr,
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[SCC_QUPV3_SE1_CLK] = &scc_qupv3_se1_clk.clkr,
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[SCC_QUPV3_SE1_CLK_SRC] = &scc_qupv3_se1_clk_src.clkr,
|
|
[SCC_QUPV3_SE2_CLK] = &scc_qupv3_se2_clk.clkr,
|
|
[SCC_QUPV3_SE2_CLK_SRC] = &scc_qupv3_se2_clk_src.clkr,
|
|
[SCC_QUPV3_SE3_CLK] = &scc_qupv3_se3_clk.clkr,
|
|
[SCC_QUPV3_SE3_CLK_SRC] = &scc_qupv3_se3_clk_src.clkr,
|
|
[SCC_QUPV3_SE4_CLK] = &scc_qupv3_se4_clk.clkr,
|
|
[SCC_QUPV3_SE4_CLK_SRC] = &scc_qupv3_se4_clk_src.clkr,
|
|
[SCC_QUPV3_SE5_CLK] = &scc_qupv3_se5_clk.clkr,
|
|
[SCC_QUPV3_SE5_CLK_SRC] = &scc_qupv3_se5_clk_src.clkr,
|
|
};
|
|
|
|
static struct clk_dfs scc_dfs_clocks[] = {
|
|
{ &scc_qupv3_se0_clk_src, DFS_ENABLE_RCG },
|
|
{ &scc_qupv3_se1_clk_src, DFS_ENABLE_RCG },
|
|
{ &scc_qupv3_se2_clk_src, DFS_ENABLE_RCG },
|
|
{ &scc_qupv3_se3_clk_src, DFS_ENABLE_RCG },
|
|
{ &scc_qupv3_se4_clk_src, DFS_ENABLE_RCG },
|
|
{ &scc_qupv3_se5_clk_src, DFS_ENABLE_RCG },
|
|
};
|
|
|
|
static const struct qcom_cc_dfs_desc scc_sm6150_dfs_desc = {
|
|
.clks = scc_dfs_clocks,
|
|
.num_clks = ARRAY_SIZE(scc_dfs_clocks),
|
|
};
|
|
|
|
static const struct regmap_config scc_sm6150_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x30000,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct qcom_cc_desc scc_sm6150_desc = {
|
|
.config = &scc_sm6150_regmap_config,
|
|
.clks = scc_sm6150_clocks,
|
|
.num_clks = ARRAY_SIZE(scc_sm6150_clocks),
|
|
};
|
|
|
|
static const struct of_device_id scc_sm6150_match_table[] = {
|
|
{ .compatible = "qcom,scc-sm6150" },
|
|
{ .compatible = "qcom,scc-sa6155" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, scc_sm6150_match_table);
|
|
|
|
static void scc_sm6150_fixup_sa6155(struct platform_device *pdev)
|
|
{
|
|
vdd_scc_cx.num_levels = VDD_NUM_SA6155;
|
|
vdd_scc_cx.cur_level = VDD_NUM_SA6155;
|
|
}
|
|
|
|
static int scc_sm6150_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
int ret;
|
|
int is_sa6155;
|
|
|
|
vdd_scc_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_scc_cx");
|
|
if (IS_ERR(vdd_scc_cx.regulator[0])) {
|
|
if (!(PTR_ERR(vdd_scc_cx.regulator[0]) == -EPROBE_DEFER))
|
|
dev_err(&pdev->dev,
|
|
"Unable to get vdd_scc_cx regulator\n");
|
|
return PTR_ERR(vdd_scc_cx.regulator[0]);
|
|
}
|
|
|
|
is_sa6155 = of_device_is_compatible(pdev->dev.of_node,
|
|
"qcom,scc-sa6155");
|
|
if (is_sa6155)
|
|
scc_sm6150_fixup_sa6155(pdev);
|
|
|
|
regmap = qcom_cc_map(pdev, &scc_sm6150_desc);
|
|
if (IS_ERR(regmap)) {
|
|
pr_err("Failed to map the scc registers\n");
|
|
return PTR_ERR(regmap);
|
|
}
|
|
|
|
ret = qcom_cc_really_probe(pdev, &scc_sm6150_desc, regmap);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register SCC clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
/* DFS clock registration */
|
|
ret = qcom_cc_register_rcg_dfs(pdev, &scc_sm6150_dfs_desc);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register with DFS!\n");
|
|
return ret;
|
|
}
|
|
|
|
if (is_sa6155)
|
|
dev_set_drvdata(&pdev->dev, regmap);
|
|
|
|
dev_info(&pdev->dev, "Registered SCC clocks\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver scc_sm6150_driver = {
|
|
.probe = scc_sm6150_probe,
|
|
.driver = {
|
|
.name = "scc-sm6150",
|
|
.of_match_table = scc_sm6150_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init scc_sm6150_init(void)
|
|
{
|
|
return platform_driver_register(&scc_sm6150_driver);
|
|
}
|
|
subsys_initcall(scc_sm6150_init);
|
|
|
|
static void __exit scc_sm6150_exit(void)
|
|
{
|
|
platform_driver_unregister(&scc_sm6150_driver);
|
|
}
|
|
module_exit(scc_sm6150_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI SCC SM6150 Driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:scc-sm6150");
|
|
|