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553 lines
14 KiB
553 lines
14 KiB
/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "clk: %s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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#include "reset.h"
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#include "clk-alpha-pll.h"
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#include "vdd-level.h"
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);
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enum {
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P_BI_TCXO,
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P_CORE_BI_PLL_TEST_SE,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_CC_PLL0_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_MAIN,
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};
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const gpu_cc_parent_names_0[] = {
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"bi_tcxo",
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"gpu_cc_pll0",
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"gpu_cc_pll1",
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"gcc_gpu_gpll0_clk_src",
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"gcc_gpu_gpll0_div_clk_src",
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"core_bi_pll_test_se",
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};
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static struct pll_vco trion_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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static struct alpha_pll_config gpu_cc_pll1_config = {
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.l = 0x1A,
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.alpha = 0xAAA,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002267,
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.config_ctl_hi1_val = 0x00000024,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000002,
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.test_ctl_hi1_val = 0x00000000,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x000000D0,
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};
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static struct clk_alpha_pll gpu_cc_pll1 = {
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.offset = 0x100,
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.vco_table = trion_vco,
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.num_vco = ARRAY_SIZE(trion_vco),
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.config = &gpu_cc_pll1_config,
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.type = TRION_PLL,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_trion_pll_ops,
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.vdd_class = &vdd_mx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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},
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},
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
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F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src_sdmshrike[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
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F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
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F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_names = gpu_cc_parent_names_0,
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.num_parents = 6,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 200000000,
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[VDD_LOW] = 500000000},
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},
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};
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static struct clk_branch gpu_cc_ahb_clk = {
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.halt_reg = 0x1078,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1078,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_crc_ahb_clk = {
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.halt_reg = 0x107c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x107c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_crc_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_apb_clk = {
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.halt_reg = 0x1088,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1088,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_apb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gmu_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gmu_clk",
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.parent_names = (const char *[]){
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"gpu_cc_gmu_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_qdss_at_clk = {
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.halt_reg = 0x1080,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1080,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_qdss_at_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_qdss_trig_clk = {
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.halt_reg = 0x1094,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1094,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_qdss_trig_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = {
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.halt_reg = 0x1084,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1084,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_qdss_tsctr_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
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.halt_reg = 0x108c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x108c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_snoc_dvm_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_aon_clk = {
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.halt_reg = 0x1004,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_aon_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_clk = {
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.halt_reg = 0x109c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x109c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_gx_gmu_clk = {
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.halt_reg = 0x1064,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1064,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_gmu_clk",
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.parent_names = (const char *[]){
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"gpu_cc_gmu_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = {
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.halt_reg = 0x105c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x105c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_qdss_tsctr_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_gx_vsense_clk = {
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.halt_reg = 0x1058,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1058,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_vsense_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_pll_test_clk = {
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.halt_reg = 0x110c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x110c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll_test_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_sleep_clk = {
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.halt_reg = 0x1090,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1090,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_sleep_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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/* Measure-only clock for gpu_cc_cx_gfx3d_clk. */
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static struct clk_dummy measure_only_gpu_cc_cx_gfx3d_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gpu_cc_cx_gfx3d_clk",
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.ops = &clk_dummy_ops,
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},
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};
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/* Measure-only clock for gpu_cc_cx_gfx3d_slv_clk. */
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static struct clk_dummy measure_only_gpu_cc_cx_gfx3d_slv_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gpu_cc_cx_gfx3d_slv_clk",
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.ops = &clk_dummy_ops,
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},
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};
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/* Measure-only clock for gpu_cc_gx_gfx3d_clk. */
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static struct clk_dummy measure_only_gpu_cc_gx_gfx3d_clk = {
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.rrate = 1000,
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.hw.init = &(struct clk_init_data){
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.name = "measure_only_gpu_cc_gx_gfx3d_clk",
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.ops = &clk_dummy_ops,
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},
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};
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struct clk_hw *gpu_cc_sm8150_hws[] = {
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[MEASURE_ONLY_GPU_CC_CX_GFX3D_CLK] =
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&measure_only_gpu_cc_cx_gfx3d_clk.hw,
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[MEASURE_ONLY_GPU_CC_CX_GFX3D_SLV_CLK] =
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&measure_only_gpu_cc_cx_gfx3d_slv_clk.hw,
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[MEASURE_ONLY_GPU_CC_GX_GFX3D_CLK] =
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&measure_only_gpu_cc_gx_gfx3d_clk.hw,
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};
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static struct clk_regmap *gpu_cc_sm8150_clocks[] = {
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[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
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[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
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[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
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[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
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[GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr,
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[GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr,
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[GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr,
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[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
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[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
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[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
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[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
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[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
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[GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr,
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[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
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[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
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[GPU_CC_PLL_TEST_CLK] = &gpu_cc_pll_test_clk.clkr,
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[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
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};
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static const struct qcom_reset_map gpu_cc_sm8150_resets[] = {
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[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
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[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
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[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
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[GPUCC_GPU_CC_SPDM_BCR] = { 0x1110 },
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[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
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};
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static const struct regmap_config gpu_cc_sm8150_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x8008,
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.fast_io = true,
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};
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static const struct qcom_cc_desc gpu_cc_sm8150_desc = {
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.config = &gpu_cc_sm8150_regmap_config,
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.clks = gpu_cc_sm8150_clocks,
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.num_clks = ARRAY_SIZE(gpu_cc_sm8150_clocks),
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.resets = gpu_cc_sm8150_resets,
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.num_resets = ARRAY_SIZE(gpu_cc_sm8150_resets),
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};
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static struct clk_regmap *gpucc_sm8150_critical_clocks[] = {
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&gpu_cc_ahb_clk.clkr,
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};
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static const struct qcom_cc_critical_desc gpucc_sm8150_critical_desc = {
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.clks = gpucc_sm8150_critical_clocks,
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.num_clks = ARRAY_SIZE(gpucc_sm8150_critical_clocks),
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};
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static const struct of_device_id gpu_cc_sm8150_match_table[] = {
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{ .compatible = "qcom,gpucc-sm8150" },
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{ .compatible = "qcom,gpucc-sdmshrike" },
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{ .compatible = "qcom,gpucc-sa8155" },
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{ }
|
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};
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MODULE_DEVICE_TABLE(of, gpu_cc_sm8150_match_table);
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|
|
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static int gpucc_sa8150_resume(struct device *dev)
|
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{
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return qcom_cc_enable_critical_clks(&gpucc_sm8150_critical_desc);
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}
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|
|
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static const struct dev_pm_ops gpucc_sa8150_pm_ops = {
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.restore_early = gpucc_sa8150_resume,
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|
};
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|
|
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static void gpu_cc_sm8150_fixup_sdmshrike(void)
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|
{
|
|
gpu_cc_gmu_clk_src.freq_tbl = ftbl_gpu_cc_gmu_clk_src_sdmshrike;
|
|
gpu_cc_gmu_clk_src.clkr.hw.init->rate_max[VDD_LOW] = 400000000;
|
|
gpu_cc_gmu_clk_src.clkr.hw.init->rate_max[VDD_LOW_L1] = 500000000;
|
|
}
|
|
|
|
static int gpu_cc_sm8150_fixup(struct platform_device *pdev)
|
|
{
|
|
const char *compat = NULL;
|
|
int compatlen = 0;
|
|
|
|
compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);
|
|
if (!compat || (compatlen <= 0))
|
|
return -EINVAL;
|
|
|
|
if (!strcmp(compat, "qcom,gpucc-sdmshrike"))
|
|
gpu_cc_sm8150_fixup_sdmshrike();
|
|
|
|
if (!strcmp(compat, "qcom,gpucc-sa8155"))
|
|
pdev->dev.driver->pm = &gpucc_sa8150_pm_ops;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gpu_cc_sm8150_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
struct clk *clk;
|
|
int i, ret = 0;
|
|
|
|
regmap = qcom_cc_map(pdev, &gpu_cc_sm8150_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
|
|
if (IS_ERR(vdd_cx.regulator[0])) {
|
|
if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER)
|
|
dev_err(&pdev->dev,
|
|
"Unable to get vdd_cx regulator\n");
|
|
return PTR_ERR(vdd_cx.regulator[0]);
|
|
}
|
|
|
|
vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
|
|
if (IS_ERR(vdd_mx.regulator[0])) {
|
|
if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER)
|
|
dev_err(&pdev->dev,
|
|
"Unable to get vdd_mx regulator\n");
|
|
return PTR_ERR(vdd_mx.regulator[0]);
|
|
}
|
|
|
|
gpu_cc_sm8150_fixup(pdev);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(gpu_cc_sm8150_hws); i++) {
|
|
clk = devm_clk_register(&pdev->dev, gpu_cc_sm8150_hws[i]);
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
}
|
|
|
|
clk_trion_pll_configure(&gpu_cc_pll1, regmap, gpu_cc_pll1.config);
|
|
|
|
ret = qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Registered GPU CC clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver gpu_cc_sm8150_driver = {
|
|
.probe = gpu_cc_sm8150_probe,
|
|
.driver = {
|
|
.name = "gpu_cc-sm8150",
|
|
.of_match_table = gpu_cc_sm8150_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init gpu_cc_sm8150_init(void)
|
|
{
|
|
return platform_driver_register(&gpu_cc_sm8150_driver);
|
|
}
|
|
subsys_initcall(gpu_cc_sm8150_init);
|
|
|
|
static void __exit gpu_cc_sm8150_exit(void)
|
|
{
|
|
platform_driver_unregister(&gpu_cc_sm8150_driver);
|
|
}
|
|
module_exit(gpu_cc_sm8150_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI GPU_CC SM8150 Driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:gpu_cc-sm8150");
|
|
|