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321 lines
11 KiB
321 lines
11 KiB
/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "clk: %s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include "clk-debug.h"
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static struct measure_clk_data debug_mux_priv = {
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.ctl_reg = 0x79004,
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.status_reg = 0x79008,
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.xo_div4_cbcr = 0x22010,
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};
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static const char *const debug_mux_parent_names[] = {
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"gcc_ahb_pcie_link_clk",
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"gcc_blsp1_ahb_clk",
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"gcc_blsp1_qup1_i2c_apps_clk",
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"gcc_blsp1_qup1_spi_apps_clk",
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"gcc_blsp1_qup2_i2c_apps_clk",
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"gcc_blsp1_qup2_spi_apps_clk",
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"gcc_blsp1_qup3_i2c_apps_clk",
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"gcc_blsp1_qup3_spi_apps_clk",
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"gcc_blsp1_qup4_i2c_apps_clk",
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"gcc_blsp1_qup4_spi_apps_clk",
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"gcc_blsp1_sleep_clk",
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"gcc_blsp1_uart1_apps_clk",
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"gcc_blsp1_uart2_apps_clk",
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"gcc_blsp1_uart3_apps_clk",
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"gcc_blsp1_uart4_apps_clk",
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"gcc_boot_rom_ahb_clk",
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"gcc_ce1_ahb_clk",
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"gcc_ce1_axi_clk",
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"gcc_ce1_clk",
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"gcc_cpuss_ahb_clk",
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"gcc_cpuss_gnoc_clk",
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"gcc_cpuss_rbcpr_clk",
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"gcc_eth_axi_clk",
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"gcc_eth_ptp_clk",
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"gcc_eth_rgmii_clk",
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"gcc_eth_slave_ahb_clk",
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"gcc_gp1_clk",
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"gcc_gp2_clk",
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"gcc_gp3_clk",
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"gcc_pcie_aux_clk",
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"gcc_pcie_cfg_ahb_clk",
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"gcc_pcie_mstr_axi_clk",
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"gcc_pcie_pipe_clk",
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"gcc_pcie_rchng_phy_clk",
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"gcc_pcie_sleep_clk",
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"gcc_pcie_slv_axi_clk",
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"gcc_pcie_slv_q2a_axi_clk",
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"gcc_pdm2_clk",
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"gcc_pdm_ahb_clk",
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"gcc_pdm_xo4_clk",
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"gcc_sdcc1_ahb_clk",
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"gcc_sdcc1_apps_clk",
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"gcc_spmi_fetcher_ahb_clk",
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"gcc_spmi_fetcher_clk",
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"gcc_sys_noc_cpuss_ahb_clk",
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"gcc_usb30_master_clk",
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"gcc_usb30_mock_utmi_clk",
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"gcc_usb30_mstr_axi_clk",
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"gcc_usb30_sleep_clk",
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"gcc_usb30_slv_ahb_clk",
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"gcc_usb3_phy_aux_clk",
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"gcc_usb3_phy_pipe_clk",
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"gcc_usb_phy_cfg_ahb2phy_clk",
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"gcc_xo_div4_clk",
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"gcc_xo_pcie_link_clk",
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"measure_only_bimc_clk",
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"measure_only_ipa_2x_clk",
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"measure_only_snoc_clk",
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"apcs_mux_clk",
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"qpic_clk",
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};
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static struct clk_debug_mux gcc_debug_mux = {
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.priv = &debug_mux_priv,
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.debug_offset = 0x79000,
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.post_div_offset = 0x29000,
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.cbcr_offset = 0x29004,
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.src_sel_mask = 0x3FF,
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.src_sel_shift = 0,
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.post_div_mask = 0xF,
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.post_div_shift = 0,
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.period_offset = 0x50,
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MUX_SRC_LIST(
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{ "gcc_ahb_pcie_link_clk", 0xCF, 4, GCC,
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0xCF, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_ahb_clk", 0x34, 4, GCC,
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0x34, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_qup1_i2c_apps_clk", 0x37, 4, GCC,
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0x37, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_qup1_spi_apps_clk", 0x36, 4, GCC,
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0x36, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_qup2_i2c_apps_clk", 0x3B, 4, GCC,
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0x3B, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_qup2_spi_apps_clk", 0x3A, 4, GCC,
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0x3A, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_qup3_i2c_apps_clk", 0x3F, 4, GCC,
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0x3F, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_qup3_spi_apps_clk", 0x3E, 4, GCC,
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0x3E, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_qup4_i2c_apps_clk", 0x43, 4, GCC,
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0x43, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_qup4_spi_apps_clk", 0x42, 4, GCC,
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0x42, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_sleep_clk", 0x35, 4, GCC,
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0x35, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_uart1_apps_clk", 0x38, 4, GCC,
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0x38, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_uart2_apps_clk", 0x3C, 4, GCC,
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0x3C, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_uart3_apps_clk", 0x40, 4, GCC,
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0x40, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_blsp1_uart4_apps_clk", 0x44, 4, GCC,
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0x44, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_boot_rom_ahb_clk", 0x4B, 4, GCC,
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0x4B, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_ce1_ahb_clk", 0x60, 4, GCC,
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0x60, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_ce1_axi_clk", 0x5F, 4, GCC,
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0x5F, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_ce1_clk", 0x5E, 4, GCC,
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0x5E, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_cpuss_ahb_clk", 0x74, 4, GCC,
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0x74, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_cpuss_gnoc_clk", 0x75, 4, GCC,
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0x75, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_cpuss_rbcpr_clk", 0x76, 4, GCC,
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0x76, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_eth_axi_clk", 0xCB, 4, GCC,
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0xCB, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_eth_ptp_clk", 0xFD, 4, GCC,
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0xFD, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_eth_rgmii_clk", 0xC9, 4, GCC,
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0xC9, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_eth_slave_ahb_clk", 0xCA, 4, GCC,
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0xCA, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_gp1_clk", 0x85, 4, GCC,
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0x85, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_gp2_clk", 0x86, 4, GCC,
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0x86, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_gp3_clk", 0x87, 4, GCC,
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0x87, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_pcie_aux_clk", 0x99, 4, GCC,
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0x99, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_pcie_cfg_ahb_clk", 0x98, 4, GCC,
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0x98, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_pcie_mstr_axi_clk", 0x97, 4, GCC,
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0x97, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_pcie_pipe_clk", 0x9A, 4, GCC,
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0x9A, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_pcie_rchng_phy_clk", 0xB9, 4, GCC,
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0xB9, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_pcie_sleep_clk", 0x9C, 4, GCC,
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0x9C, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_pcie_slv_axi_clk", 0x96, 4, GCC,
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0x96, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_pcie_slv_q2a_axi_clk", 0x95, 4, GCC,
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0x95, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_pdm2_clk", 0x48, 4, GCC,
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0x48, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_pdm_ahb_clk", 0x46, 4, GCC,
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0x46, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_pdm_xo4_clk", 0x47, 4, GCC,
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0x47, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_sdcc1_ahb_clk", 0x33, 4, GCC,
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0x33, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_sdcc1_apps_clk", 0x32, 4, GCC,
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0x32, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_spmi_fetcher_ahb_clk", 0xB5, 4, GCC,
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0xB5, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_spmi_fetcher_clk", 0xB4, 4, GCC,
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0xB4, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_sys_noc_cpuss_ahb_clk", 0x10B, 4, GCC,
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0x10B, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_usb30_master_clk", 0x28, 4, GCC,
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0x28, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_usb30_mock_utmi_clk", 0x2A, 4, GCC,
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0x2A, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_usb30_mstr_axi_clk", 0x4F, 4, GCC,
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0x4F, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_usb30_sleep_clk", 0x29, 4, GCC,
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0x29, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_usb30_slv_ahb_clk", 0x6B, 4, GCC,
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0x6B, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_usb3_phy_aux_clk", 0x2B, 4, GCC,
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0x2B, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_usb3_phy_pipe_clk", 0x2D, 4, GCC,
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0x2D, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_usb_phy_cfg_ahb2phy_clk", 0x31, 4, GCC,
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0x31, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_xo_div4_clk", 0x63, 4, GCC,
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0x63, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "gcc_xo_pcie_link_clk", 0x77, 4, GCC,
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0x77, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "measure_only_bimc_clk", 0x73, 4, MC_CC,
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0x73, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "measure_only_ipa_2x_clk", 0xAC, 4, GCC,
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0xAC, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "measure_only_snoc_clk", 0x109, 4, GCC,
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0x109, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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{ "apcs_mux_clk", 0x7C, 4, CPU_CC,
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0x3, 0x7, 0x3, 0x0, 0, 1, 0, 0, U32_MAX, 1 },
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{ "qpic_clk", 0xB1, 4, GCC,
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0xB1, 0x3FF, 0, 0xF, 0, 4, 0x79000, 0x29000, 0x29004 },
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),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_debug_mux",
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.ops = &clk_debug_mux_ops,
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.parent_names = debug_mux_parent_names,
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.num_parents = ARRAY_SIZE(debug_mux_parent_names),
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.flags = CLK_IS_MEASURE,
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},
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};
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static const struct of_device_id clk_debug_match_table[] = {
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{ .compatible = "qcom,debugcc-sdxprairie" },
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{ }
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};
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static int map_debug_bases(struct platform_device *pdev, char *base, int cc)
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{
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if (!of_get_property(pdev->dev.of_node, base, NULL))
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return -ENODEV;
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gcc_debug_mux.regmap[cc] =
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syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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base);
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if (IS_ERR(gcc_debug_mux.regmap[cc])) {
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pr_err("Failed to map %s (ret=%ld)\n", base,
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PTR_ERR(gcc_debug_mux.regmap[cc]));
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return PTR_ERR(gcc_debug_mux.regmap[cc]);
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}
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return 0;
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}
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static int clk_debug_sdxprairie_probe(struct platform_device *pdev)
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{
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struct clk *clk;
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int ret = 0;
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clk = devm_clk_get(&pdev->dev, "xo_clk_src");
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Unable to get xo clock\n");
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return PTR_ERR(clk);
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}
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debug_mux_priv.cxo = clk;
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gcc_debug_mux.regmap = devm_kcalloc(&pdev->dev, MAX_NUM_CC,
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sizeof(*gcc_debug_mux.regmap), GFP_KERNEL);
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if (!gcc_debug_mux.regmap)
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return -ENOMEM;
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ret = map_debug_bases(pdev, "qcom,gcc", GCC);
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if (ret)
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return ret;
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ret = map_debug_bases(pdev, "qcom,cpucc", CPU_CC);
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if (ret)
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return ret;
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ret = map_debug_bases(pdev, "qcom,mccc", MC_CC);
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if (ret)
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return ret;
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clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "Unable to register GCC debug mux\n");
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return PTR_ERR(clk);
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}
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ret = clk_debug_measure_register(&gcc_debug_mux.hw);
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if (ret)
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dev_err(&pdev->dev, "Could not register Measure clock\n");
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return ret;
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}
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static struct platform_driver clk_debug_driver = {
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.probe = clk_debug_sdxprairie_probe,
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.driver = {
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.name = "debugcc-sdxprairie",
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.of_match_table = clk_debug_match_table,
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.owner = THIS_MODULE,
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},
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};
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int __init clk_debug_sdxprairie_init(void)
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{
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return platform_driver_register(&clk_debug_driver);
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}
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fs_initcall(clk_debug_sdxprairie_init);
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MODULE_DESCRIPTION("QTI DEBUG CC SDXPRAIRIE Driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:debugcc-sdxprairie");
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