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145 lines
4.2 KiB
145 lines
4.2 KiB
/*
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* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_CLK_DEBUG_H__
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#define __QCOM_CLK_DEBUG_H__
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#include "../clk.h"
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/* Debugfs Measure Clocks */
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/**
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* struct measure_clk_data - Structure of clk measure
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*
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* @cxo: XO clock.
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* @xo_div4_cbcr: offset of debug XO/4 div register.
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* @ctl_reg: offset of debug control register.
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* @status_reg: offset of debug status register.
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* @cbcr_offset: branch register to turn on debug mux.
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*/
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struct measure_clk_data {
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struct clk *cxo;
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u32 ctl_reg;
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u32 status_reg;
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u32 xo_div4_cbcr;
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};
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/**
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* List of Debug clock controllers.
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*/
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enum debug_cc {
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GCC,
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CAM_CC,
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DISP_CC,
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NPU_CC,
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GPU_CC,
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VIDEO_CC,
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CPU_CC,
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MC_CC,
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MAX_NUM_CC,
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};
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/**
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* struct clk_src - Structure of clock source for debug mux
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*
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* @parents: clock name to be used as parent for debug mux.
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* @prim_mux_sel: debug mux index at global clock controller.
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* @prim_mux_div_val: PLL post-divider setting for the primary mux.
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* @dbg_cc: indicates the clock controller for recursive debug
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* clock controllers.
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* @dbg_cc_mux_sel: indicates the debug mux index at recursive debug mux.
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* @mux_sel_mask: indicates the mask for the mux selection.
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* @mux_sel_shift: indicates the shift required for mux selection.
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* @post_div_mask: indicates the post div mask to be used at recursive
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* debug mux.
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* @post_div_shift: indicates the shift required for post divider
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* configuration.
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* @post_div_val: indicates the post div value to be used at recursive
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* debug mux.
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* @mux_offset: the debug mux offset.
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* @post_div_offset: register with post-divider settings for the debug mux.
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* @cbcr_offset: branch register to turn on debug mux.
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* @misc_div_val: includes any pre-set dividers in the measurement logic.
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*/
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struct clk_src {
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const char *parents;
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int prim_mux_sel;
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u32 prim_mux_div_val;
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enum debug_cc dbg_cc;
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int dbg_cc_mux_sel;
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u32 mux_sel_mask;
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u32 mux_sel_shift;
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u32 post_div_mask;
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u32 post_div_shift;
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u32 post_div_val;
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u32 mux_offset;
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u32 post_div_offset;
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u32 cbcr_offset;
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u32 misc_div_val;
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};
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#define MUX_SRC_LIST(...) \
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.parent = (struct clk_src[]){__VA_ARGS__}, \
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.num_parents = ARRAY_SIZE(((struct clk_src[]){__VA_ARGS__}))
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/**
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* struct clk_debug_mux - Structure of clock debug mux
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*
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* @parent: structure of clk_src
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* @num_parents: number of parents
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* @regmap: regmaps of debug mux
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* @priv: private measure_clk_data to be used by debug mux
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* @en_mask: indicates the enable bit mask at global clock
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* controller debug mux.
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* @debug_offset: debug mux offset.
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* @post_div_offset: register with post-divider settings for the debug mux.
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* @cbcr_offset: branch register to turn on debug mux.
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* @src_sel_mask: indicates the mask to be used for src selection in
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primary mux.
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* @src_sel_shift: indicates the shift required for source selection in
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primary mux.
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* @post_div_mask: indicates the post div mask to be used for the primary
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mux.
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* @post_div_shift: indicates the shift required for post divider
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selection in primary mux.
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* @period_offset: offset of the period register used to read to determine
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the mc clock period
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* @hw: handle between common and hardware-specific interfaces.
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*/
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struct clk_debug_mux {
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struct clk_src *parent;
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int num_parents;
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struct regmap **regmap;
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void *priv;
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u32 en_mask;
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u32 debug_offset;
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u32 post_div_offset;
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u32 cbcr_offset;
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u32 src_sel_mask;
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u32 src_sel_shift;
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u32 post_div_mask;
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u32 post_div_shift;
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u32 period_offset;
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u32 bus_cl_id;
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struct clk_hw hw;
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};
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#define to_clk_measure(_hw) container_of((_hw), struct clk_debug_mux, hw)
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extern const struct clk_ops clk_debug_mux_ops;
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int clk_debug_measure_register(struct clk_hw *hw);
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int clk_debug_measure_add(struct clk_hw *hw, struct dentry *dentry);
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void clk_debug_bus_vote(struct clk_hw *hw, bool enable);
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#endif
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