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474 lines
13 KiB
474 lines
13 KiB
/*******************************************************************************
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This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
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developing this code.
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This contains the functions to handle the dma and descriptors.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include "dwmac1000.h"
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#include "dwmac_dma.h"
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static int dwmac1000_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
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u32 dma_rx)
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{
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u32 value = readl(ioaddr + DMA_BUS_MODE);
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/* DMA SW reset */
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value |= DMA_BUS_MODE_SFT_RESET;
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writel(value, ioaddr + DMA_BUS_MODE);
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do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
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value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL |
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((pbl << DMA_BUS_MODE_PBL_SHIFT) |
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(pbl << DMA_BUS_MODE_RPBL_SHIFT));
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#ifdef CONFIG_STMMAC_DA
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value |= DMA_BUS_MODE_DA; /* Rx has priority over tx */
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#endif
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writel(value, ioaddr + DMA_BUS_MODE);
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/* Mask interrupts by writing to CSR7 */
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writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
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/* The base address of the RX/TX descriptor lists must be written into
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* DMA CSR3 and CSR4, respectively. */
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writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
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writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
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return 0;
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}
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/* Transmit FIFO flush operation */
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static void dwmac1000_flush_tx_fifo(unsigned long ioaddr)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
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do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
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}
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static void dwmac1000_dma_operation_mode(unsigned long ioaddr, int txmode,
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int rxmode)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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if (txmode == SF_DMA_MODE) {
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DBG(KERN_DEBUG "GMAC: enabling TX store and forward mode\n");
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/* Transmit COE type 2 cannot be done in cut-through mode. */
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csr6 |= DMA_CONTROL_TSF;
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/* Operating on second frame increase the performance
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* especially when transmit store-and-forward is used.*/
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csr6 |= DMA_CONTROL_OSF;
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} else {
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DBG(KERN_DEBUG "GMAC: disabling TX store and forward mode"
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" (threshold = %d)\n", txmode);
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csr6 &= ~DMA_CONTROL_TSF;
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csr6 &= DMA_CONTROL_TC_TX_MASK;
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/* Set the transmit threshold */
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if (txmode <= 32)
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csr6 |= DMA_CONTROL_TTC_32;
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else if (txmode <= 64)
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csr6 |= DMA_CONTROL_TTC_64;
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else if (txmode <= 128)
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csr6 |= DMA_CONTROL_TTC_128;
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else if (txmode <= 192)
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csr6 |= DMA_CONTROL_TTC_192;
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else
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csr6 |= DMA_CONTROL_TTC_256;
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}
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if (rxmode == SF_DMA_MODE) {
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DBG(KERN_DEBUG "GMAC: enabling RX store and forward mode\n");
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csr6 |= DMA_CONTROL_RSF;
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} else {
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DBG(KERN_DEBUG "GMAC: disabling RX store and forward mode"
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" (threshold = %d)\n", rxmode);
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csr6 &= ~DMA_CONTROL_RSF;
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csr6 &= DMA_CONTROL_TC_RX_MASK;
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if (rxmode <= 32)
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csr6 |= DMA_CONTROL_RTC_32;
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else if (rxmode <= 64)
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csr6 |= DMA_CONTROL_RTC_64;
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else if (rxmode <= 96)
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csr6 |= DMA_CONTROL_RTC_96;
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else
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csr6 |= DMA_CONTROL_RTC_128;
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}
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writel(csr6, ioaddr + DMA_CONTROL);
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return;
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}
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/* Not yet implemented --- no RMON module */
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static void dwmac1000_dma_diagnostic_fr(void *data,
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struct stmmac_extra_stats *x, unsigned long ioaddr)
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{
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return;
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}
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static void dwmac1000_dump_dma_regs(unsigned long ioaddr)
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{
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int i;
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pr_info(" DMA registers\n");
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for (i = 0; i < 22; i++) {
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if ((i < 9) || (i > 17)) {
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int offset = i * 4;
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pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
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(DMA_BUS_MODE + offset),
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readl(ioaddr + DMA_BUS_MODE + offset));
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}
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}
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return;
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}
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static int dwmac1000_get_tx_frame_status(void *data,
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struct stmmac_extra_stats *x,
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struct dma_desc *p, unsigned long ioaddr)
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{
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int ret = 0;
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struct net_device_stats *stats = (struct net_device_stats *)data;
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if (unlikely(p->des01.etx.error_summary)) {
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DBG(KERN_ERR "GMAC TX error... 0x%08x\n", p->des01.etx);
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if (unlikely(p->des01.etx.jabber_timeout)) {
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DBG(KERN_ERR "\tjabber_timeout error\n");
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x->tx_jabber++;
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}
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if (unlikely(p->des01.etx.frame_flushed)) {
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DBG(KERN_ERR "\tframe_flushed error\n");
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x->tx_frame_flushed++;
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dwmac1000_flush_tx_fifo(ioaddr);
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}
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if (unlikely(p->des01.etx.loss_carrier)) {
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DBG(KERN_ERR "\tloss_carrier error\n");
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x->tx_losscarrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely(p->des01.etx.no_carrier)) {
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DBG(KERN_ERR "\tno_carrier error\n");
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x->tx_carrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely(p->des01.etx.late_collision)) {
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DBG(KERN_ERR "\tlate_collision error\n");
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stats->collisions += p->des01.etx.collision_count;
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}
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if (unlikely(p->des01.etx.excessive_collisions)) {
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DBG(KERN_ERR "\texcessive_collisions\n");
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stats->collisions += p->des01.etx.collision_count;
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}
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if (unlikely(p->des01.etx.excessive_deferral)) {
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DBG(KERN_INFO "\texcessive tx_deferral\n");
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x->tx_deferred++;
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}
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if (unlikely(p->des01.etx.underflow_error)) {
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DBG(KERN_ERR "\tunderflow error\n");
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dwmac1000_flush_tx_fifo(ioaddr);
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x->tx_underflow++;
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}
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if (unlikely(p->des01.etx.ip_header_error)) {
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DBG(KERN_ERR "\tTX IP header csum error\n");
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x->tx_ip_header_error++;
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}
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if (unlikely(p->des01.etx.payload_error)) {
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DBG(KERN_ERR "\tAddr/Payload csum error\n");
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x->tx_payload_error++;
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dwmac1000_flush_tx_fifo(ioaddr);
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}
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ret = -1;
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}
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if (unlikely(p->des01.etx.deferred)) {
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DBG(KERN_INFO "GMAC TX status: tx deferred\n");
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x->tx_deferred++;
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}
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#ifdef STMMAC_VLAN_TAG_USED
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if (p->des01.etx.vlan_frame) {
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DBG(KERN_INFO "GMAC TX status: VLAN frame\n");
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x->tx_vlan++;
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}
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#endif
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return ret;
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}
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static int dwmac1000_get_tx_len(struct dma_desc *p)
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{
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return p->des01.etx.buffer1_size;
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}
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static int dwmac1000_coe_rdes0(int ipc_err, int type, int payload_err)
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{
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int ret = good_frame;
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u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
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/* bits 5 7 0 | Frame status
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* ----------------------------------------------------------
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* 0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
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* 1 0 0 | IPv4/6 No CSUM errorS.
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* 1 0 1 | IPv4/6 CSUM PAYLOAD error
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* 1 1 0 | IPv4/6 CSUM IP HR error
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* 1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS
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* 0 0 1 | IPv4/6 unsupported IP PAYLOAD
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* 0 1 1 | COE bypassed.. no IPv4/6 frame
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* 0 1 0 | Reserved.
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*/
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if (status == 0x0) {
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DBG(KERN_INFO "RX Des0 status: IEEE 802.3 Type frame.\n");
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ret = good_frame;
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} else if (status == 0x4) {
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DBG(KERN_INFO "RX Des0 status: IPv4/6 No CSUM errorS.\n");
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ret = good_frame;
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} else if (status == 0x5) {
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DBG(KERN_ERR "RX Des0 status: IPv4/6 Payload Error.\n");
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ret = csum_none;
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} else if (status == 0x6) {
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DBG(KERN_ERR "RX Des0 status: IPv4/6 Header Error.\n");
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ret = csum_none;
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} else if (status == 0x7) {
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DBG(KERN_ERR
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"RX Des0 status: IPv4/6 Header and Payload Error.\n");
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ret = csum_none;
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} else if (status == 0x1) {
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DBG(KERN_ERR
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"RX Des0 status: IPv4/6 unsupported IP PAYLOAD.\n");
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ret = discard_frame;
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} else if (status == 0x3) {
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DBG(KERN_ERR "RX Des0 status: No IPv4, IPv6 frame.\n");
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ret = discard_frame;
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}
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return ret;
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}
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static int dwmac1000_get_rx_frame_status(void *data,
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struct stmmac_extra_stats *x, struct dma_desc *p)
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{
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int ret = good_frame;
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struct net_device_stats *stats = (struct net_device_stats *)data;
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if (unlikely(p->des01.erx.error_summary)) {
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DBG(KERN_ERR "GMAC RX Error Summary... 0x%08x\n", p->des01.erx);
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if (unlikely(p->des01.erx.descriptor_error)) {
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DBG(KERN_ERR "\tdescriptor error\n");
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x->rx_desc++;
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stats->rx_length_errors++;
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}
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if (unlikely(p->des01.erx.overflow_error)) {
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DBG(KERN_ERR "\toverflow error\n");
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x->rx_gmac_overflow++;
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}
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if (unlikely(p->des01.erx.ipc_csum_error))
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DBG(KERN_ERR "\tIPC Csum Error/Giant frame\n");
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if (unlikely(p->des01.erx.late_collision)) {
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DBG(KERN_ERR "\tlate_collision error\n");
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stats->collisions++;
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stats->collisions++;
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}
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if (unlikely(p->des01.erx.receive_watchdog)) {
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DBG(KERN_ERR "\treceive_watchdog error\n");
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x->rx_watchdog++;
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}
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if (unlikely(p->des01.erx.error_gmii)) {
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DBG(KERN_ERR "\tReceive Error\n");
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x->rx_mii++;
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}
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if (unlikely(p->des01.erx.crc_error)) {
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DBG(KERN_ERR "\tCRC error\n");
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x->rx_crc++;
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stats->rx_crc_errors++;
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}
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ret = discard_frame;
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}
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/* After a payload csum error, the ES bit is set.
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* It doesn't match with the information reported into the databook.
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* At any rate, we need to understand if the CSUM hw computation is ok
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* and report this info to the upper layers. */
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ret = dwmac1000_coe_rdes0(p->des01.erx.ipc_csum_error,
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p->des01.erx.frame_type, p->des01.erx.payload_csum_error);
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if (unlikely(p->des01.erx.dribbling)) {
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DBG(KERN_ERR "GMAC RX: dribbling error\n");
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ret = discard_frame;
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}
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if (unlikely(p->des01.erx.sa_filter_fail)) {
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DBG(KERN_ERR "GMAC RX : Source Address filter fail\n");
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x->sa_rx_filter_fail++;
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ret = discard_frame;
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}
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if (unlikely(p->des01.erx.da_filter_fail)) {
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DBG(KERN_ERR "GMAC RX : Destination Address filter fail\n");
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x->da_rx_filter_fail++;
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ret = discard_frame;
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}
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if (unlikely(p->des01.erx.length_error)) {
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DBG(KERN_ERR "GMAC RX: length_error error\n");
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x->rx_length++;
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ret = discard_frame;
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}
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#ifdef STMMAC_VLAN_TAG_USED
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if (p->des01.erx.vlan_tag) {
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DBG(KERN_INFO "GMAC RX: VLAN frame tagged\n");
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x->rx_vlan++;
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}
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#endif
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return ret;
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}
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static void dwmac1000_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
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int disable_rx_ic)
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{
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int i;
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for (i = 0; i < ring_size; i++) {
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p->des01.erx.own = 1;
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p->des01.erx.buffer1_size = BUF_SIZE_8KiB - 1;
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/* To support jumbo frames */
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p->des01.erx.buffer2_size = BUF_SIZE_8KiB - 1;
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if (i == ring_size - 1)
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p->des01.erx.end_ring = 1;
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if (disable_rx_ic)
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p->des01.erx.disable_ic = 1;
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p++;
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}
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return;
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}
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static void dwmac1000_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
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{
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int i;
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for (i = 0; i < ring_size; i++) {
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p->des01.etx.own = 0;
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if (i == ring_size - 1)
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p->des01.etx.end_ring = 1;
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p++;
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}
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return;
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}
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static int dwmac1000_get_tx_owner(struct dma_desc *p)
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{
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return p->des01.etx.own;
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}
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static int dwmac1000_get_rx_owner(struct dma_desc *p)
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{
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return p->des01.erx.own;
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}
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static void dwmac1000_set_tx_owner(struct dma_desc *p)
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{
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p->des01.etx.own = 1;
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}
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static void dwmac1000_set_rx_owner(struct dma_desc *p)
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{
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p->des01.erx.own = 1;
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}
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static int dwmac1000_get_tx_ls(struct dma_desc *p)
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{
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return p->des01.etx.last_segment;
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}
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static void dwmac1000_release_tx_desc(struct dma_desc *p)
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{
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int ter = p->des01.etx.end_ring;
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memset(p, 0, sizeof(struct dma_desc));
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p->des01.etx.end_ring = ter;
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return;
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}
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static void dwmac1000_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
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int csum_flag)
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{
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p->des01.etx.first_segment = is_fs;
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if (unlikely(len > BUF_SIZE_4KiB)) {
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p->des01.etx.buffer1_size = BUF_SIZE_4KiB;
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p->des01.etx.buffer2_size = len - BUF_SIZE_4KiB;
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} else {
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p->des01.etx.buffer1_size = len;
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}
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if (likely(csum_flag))
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p->des01.etx.checksum_insertion = cic_full;
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}
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static void dwmac1000_clear_tx_ic(struct dma_desc *p)
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{
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p->des01.etx.interrupt = 0;
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}
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static void dwmac1000_close_tx_desc(struct dma_desc *p)
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{
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p->des01.etx.last_segment = 1;
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p->des01.etx.interrupt = 1;
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}
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static int dwmac1000_get_rx_frame_len(struct dma_desc *p)
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{
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return p->des01.erx.frame_length;
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}
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struct stmmac_dma_ops dwmac1000_dma_ops = {
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.init = dwmac1000_dma_init,
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.dump_regs = dwmac1000_dump_dma_regs,
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.dma_mode = dwmac1000_dma_operation_mode,
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.dma_diagnostic_fr = dwmac1000_dma_diagnostic_fr,
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.enable_dma_transmission = dwmac_enable_dma_transmission,
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.enable_dma_irq = dwmac_enable_dma_irq,
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.disable_dma_irq = dwmac_disable_dma_irq,
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.start_tx = dwmac_dma_start_tx,
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.stop_tx = dwmac_dma_stop_tx,
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.start_rx = dwmac_dma_start_rx,
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.stop_rx = dwmac_dma_stop_rx,
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.dma_interrupt = dwmac_dma_interrupt,
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};
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struct stmmac_desc_ops dwmac1000_desc_ops = {
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.tx_status = dwmac1000_get_tx_frame_status,
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.rx_status = dwmac1000_get_rx_frame_status,
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.get_tx_len = dwmac1000_get_tx_len,
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.init_rx_desc = dwmac1000_init_rx_desc,
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.init_tx_desc = dwmac1000_init_tx_desc,
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.get_tx_owner = dwmac1000_get_tx_owner,
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.get_rx_owner = dwmac1000_get_rx_owner,
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.release_tx_desc = dwmac1000_release_tx_desc,
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.prepare_tx_desc = dwmac1000_prepare_tx_desc,
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.clear_tx_ic = dwmac1000_clear_tx_ic,
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.close_tx_desc = dwmac1000_close_tx_desc,
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.get_tx_ls = dwmac1000_get_tx_ls,
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.set_tx_owner = dwmac1000_set_tx_owner,
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.set_rx_owner = dwmac1000_set_rx_owner,
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.get_rx_frame_len = dwmac1000_get_rx_frame_len,
|
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};
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|