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1164 lines
31 KiB
1164 lines
31 KiB
/*
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* Xilinx SystemACE device driver
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*
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* Copyright 2007 Secret Lab Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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/*
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* The SystemACE chip is designed to configure FPGAs by loading an FPGA
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* bitstream from a file on a CF card and squirting it into FPGAs connected
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* to the SystemACE JTAG chain. It also has the advantage of providing an
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* MPU interface which can be used to control the FPGA configuration process
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* and to use the attached CF card for general purpose storage.
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*
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* This driver is a block device driver for the SystemACE.
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*
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* Initialization:
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* The driver registers itself as a platform_device driver at module
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* load time. The platform bus will take care of calling the
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* ace_probe() method for all SystemACE instances in the system. Any
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* number of SystemACE instances are supported. ace_probe() calls
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* ace_setup() which initialized all data structures, reads the CF
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* id structure and registers the device.
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*
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* Processing:
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* Just about all of the heavy lifting in this driver is performed by
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* a Finite State Machine (FSM). The driver needs to wait on a number
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* of events; some raised by interrupts, some which need to be polled
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* for. Describing all of the behaviour in a FSM seems to be the
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* easiest way to keep the complexity low and make it easy to
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* understand what the driver is doing. If the block ops or the
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* request function need to interact with the hardware, then they
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* simply need to flag the request and kick of FSM processing.
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*
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* The FSM itself is atomic-safe code which can be run from any
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* context. The general process flow is:
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* 1. obtain the ace->lock spinlock.
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* 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is
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* cleared.
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* 3. release the lock.
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*
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* Individual states do not sleep in any way. If a condition needs to
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* be waited for then the state much clear the fsm_continue flag and
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* either schedule the FSM to be run again at a later time, or expect
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* an interrupt to call the FSM when the desired condition is met.
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*
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* In normal operation, the FSM is processed at interrupt context
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* either when the driver's tasklet is scheduled, or when an irq is
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* raised by the hardware. The tasklet can be scheduled at any time.
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* The request method in particular schedules the tasklet when a new
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* request has been indicated by the block layer. Once started, the
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* FSM proceeds as far as it can processing the request until it
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* needs on a hardware event. At this point, it must yield execution.
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*
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* A state has two options when yielding execution:
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* 1. ace_fsm_yield()
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* - Call if need to poll for event.
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* - clears the fsm_continue flag to exit the processing loop
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* - reschedules the tasklet to run again as soon as possible
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* 2. ace_fsm_yieldirq()
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* - Call if an irq is expected from the HW
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* - clears the fsm_continue flag to exit the processing loop
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* - does not reschedule the tasklet so the FSM will not be processed
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* again until an irq is received.
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* After calling a yield function, the state must return control back
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* to the FSM main loop.
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*
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* Additionally, the driver maintains a kernel timer which can process
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* the FSM. If the FSM gets stalled, typically due to a missed
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* interrupt, then the kernel timer will expire and the driver can
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* continue where it left off.
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*
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* To Do:
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* - Add FPGA configuration control interface.
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* - Request major number from lanana
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/platform_device.h>
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MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
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MODULE_DESCRIPTION("Xilinx SystemACE device driver");
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MODULE_LICENSE("GPL");
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/* SystemACE register definitions */
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#define ACE_BUSMODE (0x00)
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#define ACE_STATUS (0x04)
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#define ACE_STATUS_CFGLOCK (0x00000001)
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#define ACE_STATUS_MPULOCK (0x00000002)
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#define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */
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#define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */
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#define ACE_STATUS_CFDETECT (0x00000010)
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#define ACE_STATUS_DATABUFRDY (0x00000020)
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#define ACE_STATUS_DATABUFMODE (0x00000040)
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#define ACE_STATUS_CFGDONE (0x00000080)
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#define ACE_STATUS_RDYFORCFCMD (0x00000100)
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#define ACE_STATUS_CFGMODEPIN (0x00000200)
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#define ACE_STATUS_CFGADDR_MASK (0x0000e000)
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#define ACE_STATUS_CFBSY (0x00020000)
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#define ACE_STATUS_CFRDY (0x00040000)
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#define ACE_STATUS_CFDWF (0x00080000)
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#define ACE_STATUS_CFDSC (0x00100000)
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#define ACE_STATUS_CFDRQ (0x00200000)
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#define ACE_STATUS_CFCORR (0x00400000)
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#define ACE_STATUS_CFERR (0x00800000)
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#define ACE_ERROR (0x08)
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#define ACE_CFGLBA (0x0c)
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#define ACE_MPULBA (0x10)
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#define ACE_SECCNTCMD (0x14)
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#define ACE_SECCNTCMD_RESET (0x0100)
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#define ACE_SECCNTCMD_IDENTIFY (0x0200)
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#define ACE_SECCNTCMD_READ_DATA (0x0300)
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#define ACE_SECCNTCMD_WRITE_DATA (0x0400)
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#define ACE_SECCNTCMD_ABORT (0x0600)
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#define ACE_VERSION (0x16)
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#define ACE_VERSION_REVISION_MASK (0x00FF)
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#define ACE_VERSION_MINOR_MASK (0x0F00)
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#define ACE_VERSION_MAJOR_MASK (0xF000)
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#define ACE_CTRL (0x18)
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#define ACE_CTRL_FORCELOCKREQ (0x0001)
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#define ACE_CTRL_LOCKREQ (0x0002)
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#define ACE_CTRL_FORCECFGADDR (0x0004)
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#define ACE_CTRL_FORCECFGMODE (0x0008)
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#define ACE_CTRL_CFGMODE (0x0010)
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#define ACE_CTRL_CFGSTART (0x0020)
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#define ACE_CTRL_CFGSEL (0x0040)
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#define ACE_CTRL_CFGRESET (0x0080)
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#define ACE_CTRL_DATABUFRDYIRQ (0x0100)
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#define ACE_CTRL_ERRORIRQ (0x0200)
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#define ACE_CTRL_CFGDONEIRQ (0x0400)
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#define ACE_CTRL_RESETIRQ (0x0800)
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#define ACE_CTRL_CFGPROG (0x1000)
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#define ACE_CTRL_CFGADDR_MASK (0xe000)
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#define ACE_FATSTAT (0x1c)
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#define ACE_NUM_MINORS 16
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#define ACE_SECTOR_SIZE (512)
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#define ACE_FIFO_SIZE (32)
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#define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE)
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struct ace_reg_ops;
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struct ace_device {
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/* driver state data */
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int id;
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int media_change;
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int users;
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struct list_head list;
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/* finite state machine data */
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struct tasklet_struct fsm_tasklet;
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uint fsm_task; /* Current activity (ACE_TASK_*) */
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uint fsm_state; /* Current state (ACE_FSM_STATE_*) */
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uint fsm_continue_flag; /* cleared to exit FSM mainloop */
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uint fsm_iter_num;
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struct timer_list stall_timer;
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/* Transfer state/result, use for both id and block request */
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struct request *req; /* request being processed */
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void *data_ptr; /* pointer to I/O buffer */
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int data_count; /* number of buffers remaining */
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int data_result; /* Result of transfer; 0 := success */
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int id_req_count; /* count of id requests */
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int id_result;
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struct completion id_completion; /* used when id req finishes */
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int in_irq;
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/* Details of hardware device */
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unsigned long physaddr;
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void *baseaddr;
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int irq;
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int bus_width; /* 0 := 8 bit; 1 := 16 bit */
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struct ace_reg_ops *reg_ops;
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int lock_count;
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/* Block device data structures */
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spinlock_t lock;
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struct device *dev;
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struct request_queue *queue;
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struct gendisk *gd;
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/* Inserted CF card parameters */
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struct hd_driveid cf_id;
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};
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static int ace_major;
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/* ---------------------------------------------------------------------
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* Low level register access
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*/
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struct ace_reg_ops {
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u16(*in) (struct ace_device * ace, int reg);
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void (*out) (struct ace_device * ace, int reg, u16 val);
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void (*datain) (struct ace_device * ace);
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void (*dataout) (struct ace_device * ace);
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};
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/* 8 Bit bus width */
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static u16 ace_in_8(struct ace_device *ace, int reg)
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{
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void *r = ace->baseaddr + reg;
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return in_8(r) | (in_8(r + 1) << 8);
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}
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static void ace_out_8(struct ace_device *ace, int reg, u16 val)
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{
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void *r = ace->baseaddr + reg;
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out_8(r, val);
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out_8(r + 1, val >> 8);
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}
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static void ace_datain_8(struct ace_device *ace)
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{
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void *r = ace->baseaddr + 0x40;
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u8 *dst = ace->data_ptr;
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int i = ACE_FIFO_SIZE;
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while (i--)
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*dst++ = in_8(r++);
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ace->data_ptr = dst;
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}
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static void ace_dataout_8(struct ace_device *ace)
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{
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void *r = ace->baseaddr + 0x40;
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u8 *src = ace->data_ptr;
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int i = ACE_FIFO_SIZE;
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while (i--)
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out_8(r++, *src++);
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ace->data_ptr = src;
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}
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static struct ace_reg_ops ace_reg_8_ops = {
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.in = ace_in_8,
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.out = ace_out_8,
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.datain = ace_datain_8,
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.dataout = ace_dataout_8,
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};
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/* 16 bit big endian bus attachment */
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static u16 ace_in_be16(struct ace_device *ace, int reg)
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{
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return in_be16(ace->baseaddr + reg);
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}
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static void ace_out_be16(struct ace_device *ace, int reg, u16 val)
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{
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out_be16(ace->baseaddr + reg, val);
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}
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static void ace_datain_be16(struct ace_device *ace)
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{
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int i = ACE_FIFO_SIZE / 2;
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u16 *dst = ace->data_ptr;
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while (i--)
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*dst++ = in_le16(ace->baseaddr + 0x40);
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ace->data_ptr = dst;
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}
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static void ace_dataout_be16(struct ace_device *ace)
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{
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int i = ACE_FIFO_SIZE / 2;
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u16 *src = ace->data_ptr;
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while (i--)
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out_le16(ace->baseaddr + 0x40, *src++);
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ace->data_ptr = src;
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}
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/* 16 bit little endian bus attachment */
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static u16 ace_in_le16(struct ace_device *ace, int reg)
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{
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return in_le16(ace->baseaddr + reg);
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}
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static void ace_out_le16(struct ace_device *ace, int reg, u16 val)
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{
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out_le16(ace->baseaddr + reg, val);
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}
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static void ace_datain_le16(struct ace_device *ace)
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{
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int i = ACE_FIFO_SIZE / 2;
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u16 *dst = ace->data_ptr;
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while (i--)
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*dst++ = in_be16(ace->baseaddr + 0x40);
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ace->data_ptr = dst;
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}
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static void ace_dataout_le16(struct ace_device *ace)
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{
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int i = ACE_FIFO_SIZE / 2;
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u16 *src = ace->data_ptr;
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while (i--)
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out_be16(ace->baseaddr + 0x40, *src++);
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ace->data_ptr = src;
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}
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static struct ace_reg_ops ace_reg_be16_ops = {
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.in = ace_in_be16,
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.out = ace_out_be16,
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.datain = ace_datain_be16,
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.dataout = ace_dataout_be16,
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};
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static struct ace_reg_ops ace_reg_le16_ops = {
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.in = ace_in_le16,
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.out = ace_out_le16,
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.datain = ace_datain_le16,
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.dataout = ace_dataout_le16,
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};
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static inline u16 ace_in(struct ace_device *ace, int reg)
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{
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return ace->reg_ops->in(ace, reg);
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}
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static inline u32 ace_in32(struct ace_device *ace, int reg)
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{
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return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16);
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}
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static inline void ace_out(struct ace_device *ace, int reg, u16 val)
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{
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ace->reg_ops->out(ace, reg, val);
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}
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static inline void ace_out32(struct ace_device *ace, int reg, u32 val)
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{
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ace_out(ace, reg, val);
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ace_out(ace, reg + 2, val >> 16);
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}
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/* ---------------------------------------------------------------------
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* Debug support functions
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*/
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#if defined(DEBUG)
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static void ace_dump_mem(void *base, int len)
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{
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const char *ptr = base;
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int i, j;
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for (i = 0; i < len; i += 16) {
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printk(KERN_INFO "%.8x:", i);
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for (j = 0; j < 16; j++) {
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if (!(j % 4))
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printk(" ");
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printk("%.2x", ptr[i + j]);
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}
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printk(" ");
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for (j = 0; j < 16; j++)
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printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.');
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printk("\n");
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}
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}
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#else
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static inline void ace_dump_mem(void *base, int len)
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{
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}
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#endif
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static void ace_dump_regs(struct ace_device *ace)
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{
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dev_info(ace->dev, " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n"
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" status:%.8x mpu_lba:%.8x busmode:%4x\n"
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" error: %.8x cfg_lba:%.8x fatstat:%.4x\n",
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ace_in32(ace, ACE_CTRL),
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ace_in(ace, ACE_SECCNTCMD),
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ace_in(ace, ACE_VERSION),
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ace_in32(ace, ACE_STATUS),
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ace_in32(ace, ACE_MPULBA),
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ace_in(ace, ACE_BUSMODE),
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ace_in32(ace, ACE_ERROR),
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ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT));
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}
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void ace_fix_driveid(struct hd_driveid *id)
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{
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#if defined(__BIG_ENDIAN)
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u16 *buf = (void *)id;
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int i;
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/* All half words have wrong byte order; swap the bytes */
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for (i = 0; i < sizeof(struct hd_driveid); i += 2, buf++)
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*buf = le16_to_cpu(*buf);
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/* Some of the data values are 32bit; swap the half words */
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id->lba_capacity = ((id->lba_capacity >> 16) & 0x0000FFFF) |
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((id->lba_capacity << 16) & 0xFFFF0000);
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id->spg = ((id->spg >> 16) & 0x0000FFFF) |
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((id->spg << 16) & 0xFFFF0000);
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#endif
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}
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/* ---------------------------------------------------------------------
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* Finite State Machine (FSM) implementation
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*/
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/* FSM tasks; used to direct state transitions */
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#define ACE_TASK_IDLE 0
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#define ACE_TASK_IDENTIFY 1
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#define ACE_TASK_READ 2
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#define ACE_TASK_WRITE 3
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#define ACE_FSM_NUM_TASKS 4
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/* FSM state definitions */
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#define ACE_FSM_STATE_IDLE 0
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#define ACE_FSM_STATE_REQ_LOCK 1
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#define ACE_FSM_STATE_WAIT_LOCK 2
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#define ACE_FSM_STATE_WAIT_CFREADY 3
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#define ACE_FSM_STATE_IDENTIFY_PREPARE 4
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#define ACE_FSM_STATE_IDENTIFY_TRANSFER 5
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#define ACE_FSM_STATE_IDENTIFY_COMPLETE 6
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#define ACE_FSM_STATE_REQ_PREPARE 7
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#define ACE_FSM_STATE_REQ_TRANSFER 8
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#define ACE_FSM_STATE_REQ_COMPLETE 9
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#define ACE_FSM_STATE_ERROR 10
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#define ACE_FSM_NUM_STATES 11
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/* Set flag to exit FSM loop and reschedule tasklet */
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static inline void ace_fsm_yield(struct ace_device *ace)
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{
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dev_dbg(ace->dev, "ace_fsm_yield()\n");
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tasklet_schedule(&ace->fsm_tasklet);
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ace->fsm_continue_flag = 0;
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}
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/* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */
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static inline void ace_fsm_yieldirq(struct ace_device *ace)
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{
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dev_dbg(ace->dev, "ace_fsm_yieldirq()\n");
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if (ace->irq == NO_IRQ)
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/* No IRQ assigned, so need to poll */
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tasklet_schedule(&ace->fsm_tasklet);
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ace->fsm_continue_flag = 0;
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}
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/* Get the next read/write request; ending requests that we don't handle */
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struct request *ace_get_next_request(struct request_queue * q)
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{
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struct request *req;
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while ((req = elv_next_request(q)) != NULL) {
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if (blk_fs_request(req))
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break;
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end_request(req, 0);
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}
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return req;
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}
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static void ace_fsm_dostate(struct ace_device *ace)
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{
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struct request *req;
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u32 status;
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u16 val;
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int count;
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int i;
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#if defined(DEBUG)
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dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n",
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ace->fsm_state, ace->id_req_count);
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#endif
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|
|
|
switch (ace->fsm_state) {
|
|
case ACE_FSM_STATE_IDLE:
|
|
/* See if there is anything to do */
|
|
if (ace->id_req_count || ace_get_next_request(ace->queue)) {
|
|
ace->fsm_iter_num++;
|
|
ace->fsm_state = ACE_FSM_STATE_REQ_LOCK;
|
|
mod_timer(&ace->stall_timer, jiffies + HZ);
|
|
if (!timer_pending(&ace->stall_timer))
|
|
add_timer(&ace->stall_timer);
|
|
break;
|
|
}
|
|
del_timer(&ace->stall_timer);
|
|
ace->fsm_continue_flag = 0;
|
|
break;
|
|
|
|
case ACE_FSM_STATE_REQ_LOCK:
|
|
if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) {
|
|
/* Already have the lock, jump to next state */
|
|
ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY;
|
|
break;
|
|
}
|
|
|
|
/* Request the lock */
|
|
val = ace_in(ace, ACE_CTRL);
|
|
ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ);
|
|
ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK;
|
|
break;
|
|
|
|
case ACE_FSM_STATE_WAIT_LOCK:
|
|
if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) {
|
|
/* got the lock; move to next state */
|
|
ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY;
|
|
break;
|
|
}
|
|
|
|
/* wait a bit for the lock */
|
|
ace_fsm_yield(ace);
|
|
break;
|
|
|
|
case ACE_FSM_STATE_WAIT_CFREADY:
|
|
status = ace_in32(ace, ACE_STATUS);
|
|
if (!(status & ACE_STATUS_RDYFORCFCMD) ||
|
|
(status & ACE_STATUS_CFBSY)) {
|
|
/* CF card isn't ready; it needs to be polled */
|
|
ace_fsm_yield(ace);
|
|
break;
|
|
}
|
|
|
|
/* Device is ready for command; determine what to do next */
|
|
if (ace->id_req_count)
|
|
ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE;
|
|
else
|
|
ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE;
|
|
break;
|
|
|
|
case ACE_FSM_STATE_IDENTIFY_PREPARE:
|
|
/* Send identify command */
|
|
ace->fsm_task = ACE_TASK_IDENTIFY;
|
|
ace->data_ptr = &ace->cf_id;
|
|
ace->data_count = ACE_BUF_PER_SECTOR;
|
|
ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY);
|
|
|
|
/* As per datasheet, put config controller in reset */
|
|
val = ace_in(ace, ACE_CTRL);
|
|
ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET);
|
|
|
|
/* irq handler takes over from this point; wait for the
|
|
* transfer to complete */
|
|
ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER;
|
|
ace_fsm_yieldirq(ace);
|
|
break;
|
|
|
|
case ACE_FSM_STATE_IDENTIFY_TRANSFER:
|
|
/* Check that the sysace is ready to receive data */
|
|
status = ace_in32(ace, ACE_STATUS);
|
|
if (status & ACE_STATUS_CFBSY) {
|
|
dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n",
|
|
ace->fsm_task, ace->fsm_iter_num,
|
|
ace->data_count);
|
|
ace_fsm_yield(ace);
|
|
break;
|
|
}
|
|
if (!(status & ACE_STATUS_DATABUFRDY)) {
|
|
ace_fsm_yield(ace);
|
|
break;
|
|
}
|
|
|
|
/* Transfer the next buffer */
|
|
ace->reg_ops->datain(ace);
|
|
ace->data_count--;
|
|
|
|
/* If there are still buffers to be transfers; jump out here */
|
|
if (ace->data_count != 0) {
|
|
ace_fsm_yieldirq(ace);
|
|
break;
|
|
}
|
|
|
|
/* transfer finished; kick state machine */
|
|
dev_dbg(ace->dev, "identify finished\n");
|
|
ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE;
|
|
break;
|
|
|
|
case ACE_FSM_STATE_IDENTIFY_COMPLETE:
|
|
ace_fix_driveid(&ace->cf_id);
|
|
ace_dump_mem(&ace->cf_id, 512); /* Debug: Dump out disk ID */
|
|
|
|
if (ace->data_result) {
|
|
/* Error occured, disable the disk */
|
|
ace->media_change = 1;
|
|
set_capacity(ace->gd, 0);
|
|
dev_err(ace->dev, "error fetching CF id (%i)\n",
|
|
ace->data_result);
|
|
} else {
|
|
ace->media_change = 0;
|
|
|
|
/* Record disk parameters */
|
|
set_capacity(ace->gd, ace->cf_id.lba_capacity);
|
|
dev_info(ace->dev, "capacity: %i sectors\n",
|
|
ace->cf_id.lba_capacity);
|
|
}
|
|
|
|
/* We're done, drop to IDLE state and notify waiters */
|
|
ace->fsm_state = ACE_FSM_STATE_IDLE;
|
|
ace->id_result = ace->data_result;
|
|
while (ace->id_req_count) {
|
|
complete(&ace->id_completion);
|
|
ace->id_req_count--;
|
|
}
|
|
break;
|
|
|
|
case ACE_FSM_STATE_REQ_PREPARE:
|
|
req = ace_get_next_request(ace->queue);
|
|
if (!req) {
|
|
ace->fsm_state = ACE_FSM_STATE_IDLE;
|
|
break;
|
|
}
|
|
|
|
/* Okay, it's a data request, set it up for transfer */
|
|
dev_dbg(ace->dev,
|
|
"request: sec=%lx hcnt=%lx, ccnt=%x, dir=%i\n",
|
|
req->sector, req->hard_nr_sectors,
|
|
req->current_nr_sectors, rq_data_dir(req));
|
|
|
|
ace->req = req;
|
|
ace->data_ptr = req->buffer;
|
|
ace->data_count = req->current_nr_sectors * ACE_BUF_PER_SECTOR;
|
|
ace_out32(ace, ACE_MPULBA, req->sector & 0x0FFFFFFF);
|
|
|
|
count = req->hard_nr_sectors;
|
|
if (rq_data_dir(req)) {
|
|
/* Kick off write request */
|
|
dev_dbg(ace->dev, "write data\n");
|
|
ace->fsm_task = ACE_TASK_WRITE;
|
|
ace_out(ace, ACE_SECCNTCMD,
|
|
count | ACE_SECCNTCMD_WRITE_DATA);
|
|
} else {
|
|
/* Kick off read request */
|
|
dev_dbg(ace->dev, "read data\n");
|
|
ace->fsm_task = ACE_TASK_READ;
|
|
ace_out(ace, ACE_SECCNTCMD,
|
|
count | ACE_SECCNTCMD_READ_DATA);
|
|
}
|
|
|
|
/* As per datasheet, put config controller in reset */
|
|
val = ace_in(ace, ACE_CTRL);
|
|
ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET);
|
|
|
|
/* Move to the transfer state. The systemace will raise
|
|
* an interrupt once there is something to do
|
|
*/
|
|
ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER;
|
|
if (ace->fsm_task == ACE_TASK_READ)
|
|
ace_fsm_yieldirq(ace); /* wait for data ready */
|
|
break;
|
|
|
|
case ACE_FSM_STATE_REQ_TRANSFER:
|
|
/* Check that the sysace is ready to receive data */
|
|
status = ace_in32(ace, ACE_STATUS);
|
|
if (status & ACE_STATUS_CFBSY) {
|
|
dev_dbg(ace->dev,
|
|
"CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n",
|
|
ace->fsm_task, ace->fsm_iter_num,
|
|
ace->req->current_nr_sectors * 16,
|
|
ace->data_count, ace->in_irq);
|
|
ace_fsm_yield(ace); /* need to poll CFBSY bit */
|
|
break;
|
|
}
|
|
if (!(status & ACE_STATUS_DATABUFRDY)) {
|
|
dev_dbg(ace->dev,
|
|
"DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n",
|
|
ace->fsm_task, ace->fsm_iter_num,
|
|
ace->req->current_nr_sectors * 16,
|
|
ace->data_count, ace->in_irq);
|
|
ace_fsm_yieldirq(ace);
|
|
break;
|
|
}
|
|
|
|
/* Transfer the next buffer */
|
|
i = 16;
|
|
if (ace->fsm_task == ACE_TASK_WRITE)
|
|
ace->reg_ops->dataout(ace);
|
|
else
|
|
ace->reg_ops->datain(ace);
|
|
ace->data_count--;
|
|
|
|
/* If there are still buffers to be transfers; jump out here */
|
|
if (ace->data_count != 0) {
|
|
ace_fsm_yieldirq(ace);
|
|
break;
|
|
}
|
|
|
|
/* bio finished; is there another one? */
|
|
i = ace->req->current_nr_sectors;
|
|
if (end_that_request_first(ace->req, 1, i)) {
|
|
/* dev_dbg(ace->dev, "next block; h=%li c=%i\n",
|
|
* ace->req->hard_nr_sectors,
|
|
* ace->req->current_nr_sectors);
|
|
*/
|
|
ace->data_ptr = ace->req->buffer;
|
|
ace->data_count = ace->req->current_nr_sectors * 16;
|
|
ace_fsm_yieldirq(ace);
|
|
break;
|
|
}
|
|
|
|
ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE;
|
|
break;
|
|
|
|
case ACE_FSM_STATE_REQ_COMPLETE:
|
|
/* Complete the block request */
|
|
blkdev_dequeue_request(ace->req);
|
|
end_that_request_last(ace->req, 1);
|
|
ace->req = NULL;
|
|
|
|
/* Finished request; go to idle state */
|
|
ace->fsm_state = ACE_FSM_STATE_IDLE;
|
|
break;
|
|
|
|
default:
|
|
ace->fsm_state = ACE_FSM_STATE_IDLE;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void ace_fsm_tasklet(unsigned long data)
|
|
{
|
|
struct ace_device *ace = (void *)data;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&ace->lock, flags);
|
|
|
|
/* Loop over state machine until told to stop */
|
|
ace->fsm_continue_flag = 1;
|
|
while (ace->fsm_continue_flag)
|
|
ace_fsm_dostate(ace);
|
|
|
|
spin_unlock_irqrestore(&ace->lock, flags);
|
|
}
|
|
|
|
static void ace_stall_timer(unsigned long data)
|
|
{
|
|
struct ace_device *ace = (void *)data;
|
|
unsigned long flags;
|
|
|
|
dev_warn(ace->dev,
|
|
"kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n",
|
|
ace->fsm_state, ace->fsm_task, ace->fsm_iter_num,
|
|
ace->data_count);
|
|
spin_lock_irqsave(&ace->lock, flags);
|
|
|
|
/* Rearm the stall timer *before* entering FSM (which may then
|
|
* delete the timer) */
|
|
mod_timer(&ace->stall_timer, jiffies + HZ);
|
|
|
|
/* Loop over state machine until told to stop */
|
|
ace->fsm_continue_flag = 1;
|
|
while (ace->fsm_continue_flag)
|
|
ace_fsm_dostate(ace);
|
|
|
|
spin_unlock_irqrestore(&ace->lock, flags);
|
|
}
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* Interrupt handling routines
|
|
*/
|
|
static int ace_interrupt_checkstate(struct ace_device *ace)
|
|
{
|
|
u32 sreg = ace_in32(ace, ACE_STATUS);
|
|
u16 creg = ace_in(ace, ACE_CTRL);
|
|
|
|
/* Check for error occurance */
|
|
if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) &&
|
|
(creg & ACE_CTRL_ERRORIRQ)) {
|
|
dev_err(ace->dev, "transfer failure\n");
|
|
ace_dump_regs(ace);
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t ace_interrupt(int irq, void *dev_id)
|
|
{
|
|
u16 creg;
|
|
struct ace_device *ace = dev_id;
|
|
|
|
/* be safe and get the lock */
|
|
spin_lock(&ace->lock);
|
|
ace->in_irq = 1;
|
|
|
|
/* clear the interrupt */
|
|
creg = ace_in(ace, ACE_CTRL);
|
|
ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ);
|
|
ace_out(ace, ACE_CTRL, creg);
|
|
|
|
/* check for IO failures */
|
|
if (ace_interrupt_checkstate(ace))
|
|
ace->data_result = -EIO;
|
|
|
|
if (ace->fsm_task == 0) {
|
|
dev_err(ace->dev,
|
|
"spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n",
|
|
ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL),
|
|
ace_in(ace, ACE_SECCNTCMD));
|
|
dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n",
|
|
ace->fsm_task, ace->fsm_state, ace->data_count);
|
|
}
|
|
|
|
/* Loop over state machine until told to stop */
|
|
ace->fsm_continue_flag = 1;
|
|
while (ace->fsm_continue_flag)
|
|
ace_fsm_dostate(ace);
|
|
|
|
/* done with interrupt; drop the lock */
|
|
ace->in_irq = 0;
|
|
spin_unlock(&ace->lock);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* Block ops
|
|
*/
|
|
static void ace_request(struct request_queue * q)
|
|
{
|
|
struct request *req;
|
|
struct ace_device *ace;
|
|
|
|
req = ace_get_next_request(q);
|
|
|
|
if (req) {
|
|
ace = req->rq_disk->private_data;
|
|
tasklet_schedule(&ace->fsm_tasklet);
|
|
}
|
|
}
|
|
|
|
static int ace_media_changed(struct gendisk *gd)
|
|
{
|
|
struct ace_device *ace = gd->private_data;
|
|
dev_dbg(ace->dev, "ace_media_changed(): %i\n", ace->media_change);
|
|
|
|
return ace->media_change;
|
|
}
|
|
|
|
static int ace_revalidate_disk(struct gendisk *gd)
|
|
{
|
|
struct ace_device *ace = gd->private_data;
|
|
unsigned long flags;
|
|
|
|
dev_dbg(ace->dev, "ace_revalidate_disk()\n");
|
|
|
|
if (ace->media_change) {
|
|
dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n");
|
|
|
|
spin_lock_irqsave(&ace->lock, flags);
|
|
ace->id_req_count++;
|
|
spin_unlock_irqrestore(&ace->lock, flags);
|
|
|
|
tasklet_schedule(&ace->fsm_tasklet);
|
|
wait_for_completion(&ace->id_completion);
|
|
}
|
|
|
|
dev_dbg(ace->dev, "revalidate complete\n");
|
|
return ace->id_result;
|
|
}
|
|
|
|
static int ace_open(struct inode *inode, struct file *filp)
|
|
{
|
|
struct ace_device *ace = inode->i_bdev->bd_disk->private_data;
|
|
unsigned long flags;
|
|
|
|
dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1);
|
|
|
|
filp->private_data = ace;
|
|
spin_lock_irqsave(&ace->lock, flags);
|
|
ace->users++;
|
|
spin_unlock_irqrestore(&ace->lock, flags);
|
|
|
|
check_disk_change(inode->i_bdev);
|
|
return 0;
|
|
}
|
|
|
|
static int ace_release(struct inode *inode, struct file *filp)
|
|
{
|
|
struct ace_device *ace = inode->i_bdev->bd_disk->private_data;
|
|
unsigned long flags;
|
|
u16 val;
|
|
|
|
dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1);
|
|
|
|
spin_lock_irqsave(&ace->lock, flags);
|
|
ace->users--;
|
|
if (ace->users == 0) {
|
|
val = ace_in(ace, ACE_CTRL);
|
|
ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ);
|
|
}
|
|
spin_unlock_irqrestore(&ace->lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
static int ace_ioctl(struct inode *inode, struct file *filp,
|
|
unsigned int cmd, unsigned long arg)
|
|
{
|
|
struct ace_device *ace = inode->i_bdev->bd_disk->private_data;
|
|
struct hd_geometry __user *geo = (struct hd_geometry __user *)arg;
|
|
struct hd_geometry g;
|
|
dev_dbg(ace->dev, "ace_ioctl()\n");
|
|
|
|
switch (cmd) {
|
|
case HDIO_GETGEO:
|
|
g.heads = ace->cf_id.heads;
|
|
g.sectors = ace->cf_id.sectors;
|
|
g.cylinders = ace->cf_id.cyls;
|
|
g.start = 0;
|
|
return copy_to_user(geo, &g, sizeof(g)) ? -EFAULT : 0;
|
|
|
|
default:
|
|
return -ENOTTY;
|
|
}
|
|
return -ENOTTY;
|
|
}
|
|
|
|
static struct block_device_operations ace_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = ace_open,
|
|
.release = ace_release,
|
|
.media_changed = ace_media_changed,
|
|
.revalidate_disk = ace_revalidate_disk,
|
|
.ioctl = ace_ioctl,
|
|
};
|
|
|
|
/* --------------------------------------------------------------------
|
|
* SystemACE device setup/teardown code
|
|
*/
|
|
static int __devinit ace_setup(struct ace_device *ace)
|
|
{
|
|
u16 version;
|
|
u16 val;
|
|
|
|
int rc;
|
|
|
|
spin_lock_init(&ace->lock);
|
|
init_completion(&ace->id_completion);
|
|
|
|
/*
|
|
* Map the device
|
|
*/
|
|
ace->baseaddr = ioremap(ace->physaddr, 0x80);
|
|
if (!ace->baseaddr)
|
|
goto err_ioremap;
|
|
|
|
if (ace->irq != NO_IRQ) {
|
|
rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace);
|
|
if (rc) {
|
|
/* Failure - fall back to polled mode */
|
|
dev_err(ace->dev, "request_irq failed\n");
|
|
ace->irq = NO_IRQ;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Initialize the state machine tasklet and stall timer
|
|
*/
|
|
tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace);
|
|
setup_timer(&ace->stall_timer, ace_stall_timer, (unsigned long)ace);
|
|
|
|
/*
|
|
* Initialize the request queue
|
|
*/
|
|
ace->queue = blk_init_queue(ace_request, &ace->lock);
|
|
if (ace->queue == NULL)
|
|
goto err_blk_initq;
|
|
blk_queue_hardsect_size(ace->queue, 512);
|
|
|
|
/*
|
|
* Allocate and initialize GD structure
|
|
*/
|
|
ace->gd = alloc_disk(ACE_NUM_MINORS);
|
|
if (!ace->gd)
|
|
goto err_alloc_disk;
|
|
|
|
ace->gd->major = ace_major;
|
|
ace->gd->first_minor = ace->id * ACE_NUM_MINORS;
|
|
ace->gd->fops = &ace_fops;
|
|
ace->gd->queue = ace->queue;
|
|
ace->gd->private_data = ace;
|
|
snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a');
|
|
|
|
/* set bus width */
|
|
if (ace->bus_width == 1) {
|
|
/* 0x0101 should work regardless of endianess */
|
|
ace_out_le16(ace, ACE_BUSMODE, 0x0101);
|
|
|
|
/* read it back to determine endianess */
|
|
if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001)
|
|
ace->reg_ops = &ace_reg_le16_ops;
|
|
else
|
|
ace->reg_ops = &ace_reg_be16_ops;
|
|
} else {
|
|
ace_out_8(ace, ACE_BUSMODE, 0x00);
|
|
ace->reg_ops = &ace_reg_8_ops;
|
|
}
|
|
|
|
/* Make sure version register is sane */
|
|
version = ace_in(ace, ACE_VERSION);
|
|
if ((version == 0) || (version == 0xFFFF))
|
|
goto err_read;
|
|
|
|
/* Put sysace in a sane state by clearing most control reg bits */
|
|
ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE |
|
|
ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ);
|
|
|
|
/* Enable interrupts */
|
|
val = ace_in(ace, ACE_CTRL);
|
|
val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ;
|
|
ace_out(ace, ACE_CTRL, val);
|
|
|
|
/* Print the identification */
|
|
dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n",
|
|
(version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff);
|
|
dev_dbg(ace->dev, "physaddr 0x%lx, mapped to 0x%p, irq=%i\n",
|
|
ace->physaddr, ace->baseaddr, ace->irq);
|
|
|
|
ace->media_change = 1;
|
|
ace_revalidate_disk(ace->gd);
|
|
|
|
/* Make the sysace device 'live' */
|
|
add_disk(ace->gd);
|
|
|
|
return 0;
|
|
|
|
err_read:
|
|
put_disk(ace->gd);
|
|
err_alloc_disk:
|
|
blk_cleanup_queue(ace->queue);
|
|
err_blk_initq:
|
|
iounmap(ace->baseaddr);
|
|
if (ace->irq != NO_IRQ)
|
|
free_irq(ace->irq, ace);
|
|
err_ioremap:
|
|
printk(KERN_INFO "xsysace: error initializing device at 0x%lx\n",
|
|
ace->physaddr);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static void __devexit ace_teardown(struct ace_device *ace)
|
|
{
|
|
if (ace->gd) {
|
|
del_gendisk(ace->gd);
|
|
put_disk(ace->gd);
|
|
}
|
|
|
|
if (ace->queue)
|
|
blk_cleanup_queue(ace->queue);
|
|
|
|
tasklet_kill(&ace->fsm_tasklet);
|
|
|
|
if (ace->irq != NO_IRQ)
|
|
free_irq(ace->irq, ace);
|
|
|
|
iounmap(ace->baseaddr);
|
|
}
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* Platform Bus Support
|
|
*/
|
|
|
|
static int __devinit ace_probe(struct device *device)
|
|
{
|
|
struct platform_device *dev = to_platform_device(device);
|
|
struct ace_device *ace;
|
|
int i;
|
|
|
|
dev_dbg(device, "ace_probe(%p)\n", device);
|
|
|
|
/*
|
|
* Allocate the ace device structure
|
|
*/
|
|
ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL);
|
|
if (!ace)
|
|
goto err_alloc;
|
|
|
|
ace->dev = device;
|
|
ace->id = dev->id;
|
|
ace->irq = NO_IRQ;
|
|
|
|
for (i = 0; i < dev->num_resources; i++) {
|
|
if (dev->resource[i].flags & IORESOURCE_MEM)
|
|
ace->physaddr = dev->resource[i].start;
|
|
if (dev->resource[i].flags & IORESOURCE_IRQ)
|
|
ace->irq = dev->resource[i].start;
|
|
}
|
|
|
|
/* FIXME: Should get bus_width from the platform_device struct */
|
|
ace->bus_width = 1;
|
|
|
|
dev_set_drvdata(&dev->dev, ace);
|
|
|
|
/* Call the bus-independant setup code */
|
|
if (ace_setup(ace) != 0)
|
|
goto err_setup;
|
|
|
|
return 0;
|
|
|
|
err_setup:
|
|
dev_set_drvdata(&dev->dev, NULL);
|
|
kfree(ace);
|
|
err_alloc:
|
|
printk(KERN_ERR "xsysace: could not initialize device\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/*
|
|
* Platform bus remove() method
|
|
*/
|
|
static int __devexit ace_remove(struct device *device)
|
|
{
|
|
struct ace_device *ace = dev_get_drvdata(device);
|
|
|
|
dev_dbg(device, "ace_remove(%p)\n", device);
|
|
|
|
if (ace) {
|
|
ace_teardown(ace);
|
|
kfree(ace);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct device_driver ace_driver = {
|
|
.name = "xsysace",
|
|
.bus = &platform_bus_type,
|
|
.probe = ace_probe,
|
|
.remove = __devexit_p(ace_remove),
|
|
};
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* Module init/exit routines
|
|
*/
|
|
static int __init ace_init(void)
|
|
{
|
|
ace_major = register_blkdev(ace_major, "xsysace");
|
|
if (ace_major <= 0) {
|
|
printk(KERN_WARNING "xsysace: register_blkdev() failed\n");
|
|
return ace_major;
|
|
}
|
|
|
|
pr_debug("Registering Xilinx SystemACE driver, major=%i\n", ace_major);
|
|
return driver_register(&ace_driver);
|
|
}
|
|
|
|
static void __exit ace_exit(void)
|
|
{
|
|
pr_debug("Unregistering Xilinx SystemACE driver\n");
|
|
driver_unregister(&ace_driver);
|
|
unregister_blkdev(ace_major, "xsysace");
|
|
}
|
|
|
|
module_init(ace_init);
|
|
module_exit(ace_exit);
|
|
|