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120 lines
3.1 KiB
120 lines
3.1 KiB
/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef IOATDMA_H
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#define IOATDMA_H
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#include <linux/dmaengine.h>
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#include "ioatdma_hw.h"
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#include <linux/init.h>
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#include <linux/dmapool.h>
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#include <linux/cache.h>
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#include <linux/pci_ids.h>
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#define IOAT_LOW_COMPLETION_MASK 0xffffffc0
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/**
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* struct ioat_device - internal representation of a IOAT device
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* @pdev: PCI-Express device
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* @reg_base: MMIO register space base address
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* @dma_pool: for allocating DMA descriptors
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* @common: embedded struct dma_device
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* @msi: Message Signaled Interrupt number
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*/
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struct ioat_device {
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struct pci_dev *pdev;
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void __iomem *reg_base;
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struct pci_pool *dma_pool;
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struct pci_pool *completion_pool;
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struct dma_device common;
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u8 msi;
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};
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/**
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* struct ioat_dma_chan - internal representation of a DMA channel
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* @device:
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* @reg_base:
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* @sw_in_use:
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* @completion:
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* @completion_low:
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* @completion_high:
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* @completed_cookie: last cookie seen completed on cleanup
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* @cookie: value of last cookie given to client
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* @last_completion:
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* @xfercap:
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* @desc_lock:
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* @free_desc:
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* @used_desc:
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* @resource:
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* @device_node:
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*/
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struct ioat_dma_chan {
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void __iomem *reg_base;
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dma_cookie_t completed_cookie;
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unsigned long last_completion;
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u32 xfercap; /* XFERCAP register value expanded out */
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spinlock_t cleanup_lock;
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spinlock_t desc_lock;
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struct list_head free_desc;
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struct list_head used_desc;
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int pending;
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struct ioat_device *device;
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struct dma_chan common;
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dma_addr_t completion_addr;
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union {
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u64 full; /* HW completion writeback */
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struct {
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u32 low;
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u32 high;
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};
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} *completion_virt;
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};
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/* wrapper around hardware descriptor format + additional software fields */
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/**
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* struct ioat_desc_sw - wrapper around hardware descriptor
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* @hw: hardware DMA descriptor
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* @node: this descriptor will either be on the free list,
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* or attached to a transaction list (async_tx.tx_list)
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* @tx_cnt: number of descriptors required to complete the transaction
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* @async_tx: the generic software descriptor for all engines
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*/
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struct ioat_desc_sw {
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struct ioat_dma_descriptor *hw;
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struct list_head node;
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int tx_cnt;
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DECLARE_PCI_UNMAP_LEN(len)
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DECLARE_PCI_UNMAP_ADDR(src)
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DECLARE_PCI_UNMAP_ADDR(dst)
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struct dma_async_tx_descriptor async_tx;
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};
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#endif /* IOATDMA_H */
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