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172 lines
5.4 KiB
172 lines
5.4 KiB
/*
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* Alchemy Semi PB1000 Referrence Board
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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*
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*/
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#ifndef __ASM_PB1000_H
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#define __ASM_PB1000_H
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/* PCMCIA PB1000 specific defines */
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#define PCMCIA_MAX_SOCK 1
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#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
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#define PB1000_PCR 0xBE000000
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# define PCR_SLOT_0_VPP0 (1<<0)
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# define PCR_SLOT_0_VPP1 (1<<1)
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# define PCR_SLOT_0_VCC0 (1<<2)
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# define PCR_SLOT_0_VCC1 (1<<3)
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# define PCR_SLOT_0_RST (1<<4)
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# define PCR_SLOT_1_VPP0 (1<<8)
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# define PCR_SLOT_1_VPP1 (1<<9)
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# define PCR_SLOT_1_VCC0 (1<<10)
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# define PCR_SLOT_1_VCC1 (1<<11)
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# define PCR_SLOT_1_RST (1<<12)
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#define PB1000_MDR 0xBE000004
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# define MDR_PI (1<<5) /* pcmcia int latch */
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# define MDR_EPI (1<<14) /* enable pcmcia int */
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# define MDR_CPI (1<<15) /* clear pcmcia int */
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#define PB1000_ACR1 0xBE000008
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# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */
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# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */
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# define ACR1_SLOT_0_READY (1<<2) /* ready */
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# define ACR1_SLOT_0_STATUS (1<<3) /* status change */
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# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */
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# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */
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# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */
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# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */
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# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */
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# define ACR1_SLOT_1_READY (1<<10) /* ready */
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# define ACR1_SLOT_1_STATUS (1<<11) /* status change */
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# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */
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# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */
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# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
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#define CPLD_AUX0 0xBE00000C
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#define CPLD_AUX1 0xBE000010
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#define CPLD_AUX2 0xBE000014
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/* Voltage levels */
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/* VPPEN1 - VPPEN0 */
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#define VPP_GND ((0<<1) | (0<<0))
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#define VPP_5V ((1<<1) | (0<<0))
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#define VPP_3V ((0<<1) | (1<<0))
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#define VPP_12V ((0<<1) | (1<<0))
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#define VPP_HIZ ((1<<1) | (1<<0))
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/* VCCEN1 - VCCEN0 */
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#define VCC_3V ((0<<1) | (1<<0))
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#define VCC_5V ((1<<1) | (0<<0))
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#define VCC_HIZ ((0<<1) | (0<<0))
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/* VPP/VCC */
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#define SET_VCC_VPP(VCC, VPP, SLOT)\
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((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
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/* PCI PB1000 specific defines */
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/* The reason these defines are here instead of au1000.h is because
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* the Au1000 does not have a PCI bus controller so the PCI implementation
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* on the some of the older Pb1000 boards was very board specific.
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*/
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#define PCI_CONFIG_BASE 0xBA020000 /* the only external slot */
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#define SDRAM_DEVID 0xBA010000
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#define SDRAM_CMD 0xBA010004
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#define SDRAM_CLASS 0xBA010008
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#define SDRAM_MISC 0xBA01000C
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#define SDRAM_MBAR 0xBA010010
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#define PCI_IO_DATA_PORT 0xBA800000
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#define PCI_IO_ADDR 0xBE00001C
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#define PCI_INT_ACK 0xBBC00000
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#define PCI_IO_READ 0xBBC00020
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#define PCI_IO_WRITE 0xBBC00030
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#define PCI_BRIDGE_CONFIG 0xBE000018
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#define PCI_IO_START 0x10000000
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#define PCI_IO_END 0x1000ffff
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#define PCI_MEM_START 0x18000000
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#define PCI_MEM_END 0x18ffffff
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#define PCI_FIRST_DEVFN 0
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#define PCI_LAST_DEVFN 1
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static inline u8 au_pci_io_readb(u32 addr)
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{
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writel(addr, PCI_IO_ADDR);
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writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
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return (readl(PCI_IO_DATA_PORT) & 0xff);
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}
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static inline u16 au_pci_io_readw(u32 addr)
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{
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writel(addr, PCI_IO_ADDR);
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writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
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return (readl(PCI_IO_DATA_PORT) & 0xffff);
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}
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static inline u32 au_pci_io_readl(u32 addr)
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{
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writel(addr, PCI_IO_ADDR);
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writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG);
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return readl(PCI_IO_DATA_PORT);
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}
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static inline void au_pci_io_writeb(u8 val, u32 addr)
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{
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writel(addr, PCI_IO_ADDR);
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writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
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writel(val, PCI_IO_DATA_PORT);
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}
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static inline void au_pci_io_writew(u16 val, u32 addr)
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{
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writel(addr, PCI_IO_ADDR);
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writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
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writel(val, PCI_IO_DATA_PORT);
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}
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static inline void au_pci_io_writel(u32 val, u32 addr)
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{
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writel(addr, PCI_IO_ADDR);
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writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG);
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writel(val, PCI_IO_DATA_PORT);
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}
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static inline void set_sdram_extbyte(void)
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{
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writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG);
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}
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static inline void set_slot_extbyte(void)
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{
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writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
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}
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#endif /* __ASM_PB1000_H */
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