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78 lines
2.8 KiB
78 lines
2.8 KiB
/*
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* include/asm-parisc/cache.h
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*/
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#ifndef __ARCH_PARISC_CACHE_H
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#define __ARCH_PARISC_CACHE_H
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#include <linux/config.h>
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/*
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* PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
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* 32-byte cachelines. The default configuration is not for SMP anyway,
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* so if you're building for SMP, you should select the appropriate
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* processor type. There is a potential livelock danger when running
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* a machine with this value set too small, but it's more probable you'll
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* just ruin performance.
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*/
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#ifdef CONFIG_PA20
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#define L1_CACHE_BYTES 64
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#define L1_CACHE_SHIFT 6
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#else
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#define L1_CACHE_BYTES 32
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#define L1_CACHE_SHIFT 5
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#endif
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#ifndef __ASSEMBLY__
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#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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extern void flush_data_cache_local(void); /* flushes local data-cache only */
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extern void flush_instruction_cache_local(void); /* flushes local code-cache only */
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#ifdef CONFIG_SMP
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extern void flush_data_cache(void); /* flushes data-cache only (all processors) */
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extern void flush_instruction_cache(void); /* flushes i-cache only (all processors) */
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#else
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#define flush_data_cache flush_data_cache_local
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#define flush_instruction_cache flush_instruction_cache_local
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#endif
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extern void parisc_cache_init(void); /* initializes cache-flushing */
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extern void flush_all_caches(void); /* flush everything (tlb & cache) */
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extern int get_cache_info(char *);
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extern void flush_user_icache_range_asm(unsigned long, unsigned long);
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extern void flush_kernel_icache_range_asm(unsigned long, unsigned long);
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extern void flush_user_dcache_range_asm(unsigned long, unsigned long);
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extern void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
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extern void flush_kernel_dcache_page(void *);
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extern void flush_kernel_icache_page(void *);
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extern void disable_sr_hashing(void); /* turns off space register hashing */
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extern void disable_sr_hashing_asm(int); /* low level support for above */
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extern void free_sid(unsigned long);
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unsigned long alloc_sid(void);
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extern void flush_user_dcache_page(unsigned long);
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extern void flush_user_icache_page(unsigned long);
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struct seq_file;
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extern void show_cache_info(struct seq_file *m);
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extern int split_tlb;
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extern int dcache_stride;
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extern int icache_stride;
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extern struct pdc_cache_info cache_info;
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#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
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#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
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#define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr));
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#endif /* ! __ASSEMBLY__ */
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/* Classes of processor wrt: disabling space register hashing */
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#define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */
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#define SRHASH_PCXL 1 /* pcxl */
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#define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */
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#endif
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