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249 lines
8.1 KiB
249 lines
8.1 KiB
#ifndef __bif_slave_defs_h
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#define __bif_slave_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/bif/rtl/bif_slave_regs.r
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* id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
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* last modfied: Mon Apr 11 16:06:34 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
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* id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope bif_slave */
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/* Register rw_slave_cfg, scope bif_slave, type rw */
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typedef struct {
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unsigned int slave_id : 3;
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unsigned int use_slave_id : 1;
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unsigned int boot_rdy : 1;
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unsigned int loopback : 1;
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unsigned int dis : 1;
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unsigned int dummy1 : 25;
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} reg_bif_slave_rw_slave_cfg;
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#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
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#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
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/* Register r_slave_mode, scope bif_slave, type r */
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typedef struct {
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unsigned int ch0_mode : 1;
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unsigned int ch1_mode : 1;
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unsigned int ch2_mode : 1;
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unsigned int ch3_mode : 1;
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unsigned int dummy1 : 28;
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} reg_bif_slave_r_slave_mode;
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#define REG_RD_ADDR_bif_slave_r_slave_mode 4
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/* Register rw_ch0_cfg, scope bif_slave, type rw */
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typedef struct {
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unsigned int rd_hold : 2;
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unsigned int access_mode : 1;
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unsigned int access_ctrl : 1;
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unsigned int data_cs : 2;
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unsigned int dummy1 : 26;
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} reg_bif_slave_rw_ch0_cfg;
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#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
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#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
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/* Register rw_ch1_cfg, scope bif_slave, type rw */
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typedef struct {
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unsigned int rd_hold : 2;
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unsigned int access_mode : 1;
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unsigned int access_ctrl : 1;
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unsigned int data_cs : 2;
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unsigned int dummy1 : 26;
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} reg_bif_slave_rw_ch1_cfg;
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#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
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#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
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/* Register rw_ch2_cfg, scope bif_slave, type rw */
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typedef struct {
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unsigned int rd_hold : 2;
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unsigned int access_mode : 1;
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unsigned int access_ctrl : 1;
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unsigned int data_cs : 2;
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unsigned int dummy1 : 26;
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} reg_bif_slave_rw_ch2_cfg;
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#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
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#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
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/* Register rw_ch3_cfg, scope bif_slave, type rw */
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typedef struct {
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unsigned int rd_hold : 2;
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unsigned int access_mode : 1;
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unsigned int access_ctrl : 1;
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unsigned int data_cs : 2;
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unsigned int dummy1 : 26;
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} reg_bif_slave_rw_ch3_cfg;
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#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
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#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
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/* Register rw_arb_cfg, scope bif_slave, type rw */
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typedef struct {
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unsigned int brin_mode : 1;
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unsigned int brout_mode : 3;
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unsigned int bg_mode : 3;
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unsigned int release : 2;
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unsigned int acquire : 1;
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unsigned int settle_time : 2;
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unsigned int dram_ctrl : 1;
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unsigned int dummy1 : 19;
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} reg_bif_slave_rw_arb_cfg;
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#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
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#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
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/* Register r_arb_stat, scope bif_slave, type r */
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typedef struct {
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unsigned int init_mode : 1;
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unsigned int mode : 1;
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unsigned int brin : 1;
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unsigned int brout : 1;
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unsigned int bg : 1;
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unsigned int dummy1 : 27;
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} reg_bif_slave_r_arb_stat;
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#define REG_RD_ADDR_bif_slave_r_arb_stat 36
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/* Register rw_intr_mask, scope bif_slave, type rw */
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typedef struct {
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unsigned int bus_release : 1;
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unsigned int bus_acquire : 1;
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unsigned int dummy1 : 30;
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} reg_bif_slave_rw_intr_mask;
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#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
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#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
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/* Register rw_ack_intr, scope bif_slave, type rw */
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typedef struct {
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unsigned int bus_release : 1;
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unsigned int bus_acquire : 1;
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unsigned int dummy1 : 30;
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} reg_bif_slave_rw_ack_intr;
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#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
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#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
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/* Register r_intr, scope bif_slave, type r */
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typedef struct {
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unsigned int bus_release : 1;
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unsigned int bus_acquire : 1;
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unsigned int dummy1 : 30;
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} reg_bif_slave_r_intr;
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#define REG_RD_ADDR_bif_slave_r_intr 72
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/* Register r_masked_intr, scope bif_slave, type r */
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typedef struct {
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unsigned int bus_release : 1;
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unsigned int bus_acquire : 1;
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unsigned int dummy1 : 30;
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} reg_bif_slave_r_masked_intr;
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#define REG_RD_ADDR_bif_slave_r_masked_intr 76
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/* Constants */
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enum {
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regk_bif_slave_active_hi = 0x00000003,
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regk_bif_slave_active_lo = 0x00000002,
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regk_bif_slave_addr = 0x00000000,
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regk_bif_slave_always = 0x00000001,
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regk_bif_slave_at_idle = 0x00000002,
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regk_bif_slave_burst_end = 0x00000003,
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regk_bif_slave_dma = 0x00000001,
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regk_bif_slave_hi = 0x00000003,
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regk_bif_slave_inv = 0x00000001,
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regk_bif_slave_lo = 0x00000002,
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regk_bif_slave_local = 0x00000001,
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regk_bif_slave_master = 0x00000000,
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regk_bif_slave_mode_reg = 0x00000001,
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regk_bif_slave_no = 0x00000000,
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regk_bif_slave_norm = 0x00000000,
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regk_bif_slave_on_access = 0x00000000,
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regk_bif_slave_rw_arb_cfg_default = 0x00000000,
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regk_bif_slave_rw_ch0_cfg_default = 0x00000000,
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regk_bif_slave_rw_ch1_cfg_default = 0x00000000,
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regk_bif_slave_rw_ch2_cfg_default = 0x00000000,
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regk_bif_slave_rw_ch3_cfg_default = 0x00000000,
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regk_bif_slave_rw_intr_mask_default = 0x00000000,
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regk_bif_slave_rw_slave_cfg_default = 0x00000000,
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regk_bif_slave_shared = 0x00000000,
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regk_bif_slave_slave = 0x00000001,
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regk_bif_slave_t0ns = 0x00000003,
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regk_bif_slave_t10ns = 0x00000002,
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regk_bif_slave_t20ns = 0x00000003,
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regk_bif_slave_t30ns = 0x00000002,
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regk_bif_slave_t40ns = 0x00000001,
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regk_bif_slave_t50ns = 0x00000000,
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regk_bif_slave_yes = 0x00000001,
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regk_bif_slave_z = 0x00000004
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};
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#endif /* __bif_slave_defs_h */
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