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180 lines
4.1 KiB
180 lines
4.1 KiB
/*
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* arch/cris/arch-v32/drivers/nandflash.c
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*
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* Copyright (c) 2007
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*
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* Derived from drivers/mtd/nand/spia.c
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* Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <arch/memmap.h>
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#include <hwregs/reg_map.h>
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#include <hwregs/reg_rdwr.h>
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#include <hwregs/pio_defs.h>
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#include <pinmux.h>
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#include <asm/io.h>
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#define MANUAL_ALE_CLE_CONTROL 1
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#define regf_ALE a0
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#define regf_CLE a1
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#define regf_NCE ce0_n
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#define CLE_BIT 10
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#define ALE_BIT 11
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#define CE_BIT 12
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struct mtd_info_wrapper {
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struct mtd_info info;
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struct nand_chip chip;
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};
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/* Bitmask for control pins */
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#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
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static struct mtd_info *crisv32_mtd;
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/*
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* hardware specific access to control-lines
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*/
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static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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unsigned long flags;
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reg_pio_rw_dout dout;
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struct nand_chip *this = mtd->priv;
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local_irq_save(flags);
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/* control bits change */
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if (ctrl & NAND_CTRL_CHANGE) {
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dout = REG_RD(pio, regi_pio, rw_dout);
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dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1;
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#if !MANUAL_ALE_CLE_CONTROL
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if (ctrl & NAND_ALE) {
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/* A0 = ALE high */
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this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
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regi_pio, rw_io_access1);
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} else if (ctrl & NAND_CLE) {
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/* A1 = CLE high */
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this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
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regi_pio, rw_io_access2);
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} else {
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/* A1 = CLE and A0 = ALE low */
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this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
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regi_pio, rw_io_access0);
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}
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#else
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dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0;
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dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0;
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#endif
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REG_WR(pio, regi_pio, rw_dout, dout);
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}
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/* command to chip */
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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local_irq_restore(flags);
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}
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/*
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* read device ready pin
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*/
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static int crisv32_device_ready(struct mtd_info *mtd)
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{
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reg_pio_r_din din = REG_RD(pio, regi_pio, r_din);
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return din.rdy;
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}
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/*
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* Main initialization routine
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*/
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struct mtd_info *__init crisv32_nand_flash_probe(void)
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{
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void __iomem *read_cs;
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void __iomem *write_cs;
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struct mtd_info_wrapper *wrapper;
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struct nand_chip *this;
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int err = 0;
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reg_pio_rw_man_ctrl man_ctrl = {
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.regf_NCE = regk_pio_yes,
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#if MANUAL_ALE_CLE_CONTROL
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.regf_ALE = regk_pio_yes,
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.regf_CLE = regk_pio_yes
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#endif
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};
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reg_pio_rw_oe oe = {
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.regf_NCE = regk_pio_yes,
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#if MANUAL_ALE_CLE_CONTROL
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.regf_ALE = regk_pio_yes,
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.regf_CLE = regk_pio_yes
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#endif
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};
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reg_pio_rw_dout dout = { .regf_NCE = 1 };
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/* Allocate pio pins to pio */
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crisv32_pinmux_alloc_fixed(pinmux_pio);
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/* Set up CE, ALE, CLE (ce0_n, a0, a1) for manual control and output */
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REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl);
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REG_WR(pio, regi_pio, rw_dout, dout);
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REG_WR(pio, regi_pio, rw_oe, oe);
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/* Allocate memory for MTD device structure and private data */
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wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL);
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if (!wrapper) {
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printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
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"device structure.\n");
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err = -ENOMEM;
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return NULL;
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}
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read_cs = write_cs = (void __iomem *)REG_ADDR(pio, regi_pio,
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rw_io_access0);
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/* Get pointer to private data */
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this = &wrapper->chip;
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crisv32_mtd = &wrapper->info;
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/* Link the private data with the MTD structure */
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crisv32_mtd->priv = this;
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/* Set address of NAND IO lines */
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this->IO_ADDR_R = read_cs;
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this->IO_ADDR_W = write_cs;
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this->cmd_ctrl = crisv32_hwcontrol;
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this->dev_ready = crisv32_device_ready;
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/* 20 us command delay time */
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this->chip_delay = 20;
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this->ecc.mode = NAND_ECC_SOFT;
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/* Enable the following for a flash based bad block table */
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/* this->options = NAND_USE_FLASH_BBT; */
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/* Scan to find existance of the device */
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if (nand_scan(crisv32_mtd, 1)) {
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err = -ENXIO;
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goto out_mtd;
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}
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return crisv32_mtd;
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out_mtd:
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kfree(wrapper);
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return NULL;
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}
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