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470 lines
11 KiB
470 lines
11 KiB
/*
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* abyss.c: Network driver for the Madge Smart 16/4 PCI Mk2 token ring card.
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*
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* Written 1999-2000 by Adam Fritzler
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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* This driver module supports the following cards:
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* - Madge Smart 16/4 PCI Mk2
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*
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* Maintainer(s):
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* AF Adam Fritzler mid@auk.cx
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*
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* Modification History:
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* 30-Dec-99 AF Split off from the tms380tr driver.
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* 22-Jan-00 AF Updated to use indirect read/writes
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* 23-Nov-00 JG New PCI API, cleanups
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*
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*
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* TODO:
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* 1. See if we can use MMIO instead of inb/outb/inw/outw
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* 2. Add support for Mk1 (has AT24 attached to the PCI
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* config registers)
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/netdevice.h>
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#include <linux/trdevice.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include "tms380tr.h"
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#include "abyss.h" /* Madge-specific constants */
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static char version[] __devinitdata =
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"abyss.c: v1.02 23/11/2000 by Adam Fritzler\n";
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#define ABYSS_IO_EXTENT 64
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static struct pci_device_id abyss_pci_tbl[] = {
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{ PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_MK2,
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PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_TOKEN_RING << 8, 0x00ffffff, },
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{ } /* Terminating entry */
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};
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MODULE_DEVICE_TABLE(pci, abyss_pci_tbl);
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MODULE_LICENSE("GPL");
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static int abyss_open(struct net_device *dev);
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static int abyss_close(struct net_device *dev);
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static void abyss_enable(struct net_device *dev);
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static int abyss_chipset_init(struct net_device *dev);
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static void abyss_read_eeprom(struct net_device *dev);
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static unsigned short abyss_setnselout_pins(struct net_device *dev);
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static void at24_writedatabyte(unsigned long regaddr, unsigned char byte);
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static int at24_sendfullcmd(unsigned long regaddr, unsigned char cmd, unsigned char addr);
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static int at24_sendcmd(unsigned long regaddr, unsigned char cmd);
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static unsigned char at24_readdatabit(unsigned long regaddr);
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static unsigned char at24_readdatabyte(unsigned long regaddr);
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static int at24_waitforack(unsigned long regaddr);
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static int at24_waitfornack(unsigned long regaddr);
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static void at24_setlines(unsigned long regaddr, unsigned char clock, unsigned char data);
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static void at24_start(unsigned long regaddr);
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static unsigned char at24_readb(unsigned long regaddr, unsigned char addr);
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static unsigned short abyss_sifreadb(struct net_device *dev, unsigned short reg)
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{
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return inb(dev->base_addr + reg);
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}
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static unsigned short abyss_sifreadw(struct net_device *dev, unsigned short reg)
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{
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return inw(dev->base_addr + reg);
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}
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static void abyss_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
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{
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outb(val, dev->base_addr + reg);
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}
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static void abyss_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
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{
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outw(val, dev->base_addr + reg);
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}
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static int __devinit abyss_attach(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int versionprinted;
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struct net_device *dev;
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struct net_local *tp;
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int i, ret, pci_irq_line;
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unsigned long pci_ioaddr;
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if (versionprinted++ == 0)
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printk("%s", version);
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if (pci_enable_device(pdev))
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return -EIO;
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/* Remove I/O space marker in bit 0. */
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pci_irq_line = pdev->irq;
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pci_ioaddr = pci_resource_start (pdev, 0);
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/* At this point we have found a valid card. */
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dev = alloc_trdev(sizeof(struct net_local));
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if (!dev)
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return -ENOMEM;
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SET_MODULE_OWNER(dev);
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if (!request_region(pci_ioaddr, ABYSS_IO_EXTENT, dev->name)) {
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ret = -EBUSY;
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goto err_out_trdev;
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}
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ret = request_irq(pdev->irq, tms380tr_interrupt, SA_SHIRQ,
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dev->name, dev);
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if (ret)
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goto err_out_region;
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dev->base_addr = pci_ioaddr;
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dev->irq = pci_irq_line;
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printk("%s: Madge Smart 16/4 PCI Mk2 (Abyss)\n", dev->name);
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printk("%s: IO: %#4lx IRQ: %d\n",
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dev->name, pci_ioaddr, dev->irq);
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/*
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* The TMS SIF registers lay 0x10 above the card base address.
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*/
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dev->base_addr += 0x10;
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ret = tmsdev_init(dev, &pdev->dev);
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if (ret) {
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printk("%s: unable to get memory for dev->priv.\n",
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dev->name);
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goto err_out_irq;
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}
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abyss_read_eeprom(dev);
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printk("%s: Ring Station Address: ", dev->name);
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printk("%2.2x", dev->dev_addr[0]);
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for (i = 1; i < 6; i++)
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printk(":%2.2x", dev->dev_addr[i]);
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printk("\n");
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tp = netdev_priv(dev);
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tp->setnselout = abyss_setnselout_pins;
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tp->sifreadb = abyss_sifreadb;
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tp->sifreadw = abyss_sifreadw;
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tp->sifwriteb = abyss_sifwriteb;
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tp->sifwritew = abyss_sifwritew;
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memcpy(tp->ProductID, "Madge PCI 16/4 Mk2", PROD_ID_SIZE + 1);
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dev->open = abyss_open;
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dev->stop = abyss_close;
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pci_set_drvdata(pdev, dev);
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SET_NETDEV_DEV(dev, &pdev->dev);
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ret = register_netdev(dev);
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if (ret)
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goto err_out_tmsdev;
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return 0;
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err_out_tmsdev:
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pci_set_drvdata(pdev, NULL);
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tmsdev_term(dev);
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err_out_irq:
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free_irq(pdev->irq, dev);
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err_out_region:
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release_region(pci_ioaddr, ABYSS_IO_EXTENT);
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err_out_trdev:
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free_netdev(dev);
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return ret;
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}
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static unsigned short abyss_setnselout_pins(struct net_device *dev)
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{
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unsigned short val = 0;
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struct net_local *tp = netdev_priv(dev);
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if(tp->DataRate == SPEED_4)
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val |= 0x01; /* Set 4Mbps */
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else
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val |= 0x00; /* Set 16Mbps */
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return val;
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}
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/*
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* The following Madge boards should use this code:
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* - Smart 16/4 PCI Mk2 (Abyss)
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* - Smart 16/4 PCI Mk1 (PCI T)
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* - Smart 16/4 Client Plus PnP (Big Apple)
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* - Smart 16/4 Cardbus Mk2
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*
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* These access an Atmel AT24 SEEPROM using their glue chip registers.
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*
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*/
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static void at24_writedatabyte(unsigned long regaddr, unsigned char byte)
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{
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int i;
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for (i = 0; i < 8; i++) {
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at24_setlines(regaddr, 0, (byte >> (7-i))&0x01);
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at24_setlines(regaddr, 1, (byte >> (7-i))&0x01);
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at24_setlines(regaddr, 0, (byte >> (7-i))&0x01);
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}
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}
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static int at24_sendfullcmd(unsigned long regaddr, unsigned char cmd, unsigned char addr)
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{
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if (at24_sendcmd(regaddr, cmd)) {
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at24_writedatabyte(regaddr, addr);
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return at24_waitforack(regaddr);
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}
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return 0;
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}
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static int at24_sendcmd(unsigned long regaddr, unsigned char cmd)
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{
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int i;
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for (i = 0; i < 10; i++) {
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at24_start(regaddr);
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at24_writedatabyte(regaddr, cmd);
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if (at24_waitforack(regaddr))
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return 1;
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}
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return 0;
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}
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static unsigned char at24_readdatabit(unsigned long regaddr)
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{
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unsigned char val;
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at24_setlines(regaddr, 0, 1);
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at24_setlines(regaddr, 1, 1);
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val = (inb(regaddr) & AT24_DATA)?1:0;
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at24_setlines(regaddr, 1, 1);
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at24_setlines(regaddr, 0, 1);
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return val;
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}
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static unsigned char at24_readdatabyte(unsigned long regaddr)
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{
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unsigned char data = 0;
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int i;
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for (i = 0; i < 8; i++) {
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data <<= 1;
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data |= at24_readdatabit(regaddr);
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}
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return data;
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}
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static int at24_waitforack(unsigned long regaddr)
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{
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int i;
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for (i = 0; i < 10; i++) {
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if ((at24_readdatabit(regaddr) & 0x01) == 0x00)
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return 1;
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}
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return 0;
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}
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static int at24_waitfornack(unsigned long regaddr)
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{
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int i;
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for (i = 0; i < 10; i++) {
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if ((at24_readdatabit(regaddr) & 0x01) == 0x01)
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return 1;
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}
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return 0;
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}
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static void at24_setlines(unsigned long regaddr, unsigned char clock, unsigned char data)
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{
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unsigned char val = AT24_ENABLE;
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if (clock)
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val |= AT24_CLOCK;
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if (data)
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val |= AT24_DATA;
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outb(val, regaddr);
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tms380tr_wait(20); /* Very necessary. */
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}
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static void at24_start(unsigned long regaddr)
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{
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at24_setlines(regaddr, 0, 1);
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at24_setlines(regaddr, 1, 1);
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at24_setlines(regaddr, 1, 0);
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at24_setlines(regaddr, 0, 1);
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}
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static unsigned char at24_readb(unsigned long regaddr, unsigned char addr)
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{
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unsigned char data = 0xff;
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if (at24_sendfullcmd(regaddr, AT24_WRITE, addr)) {
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if (at24_sendcmd(regaddr, AT24_READ)) {
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data = at24_readdatabyte(regaddr);
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if (!at24_waitfornack(regaddr))
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data = 0xff;
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}
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}
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return data;
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}
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/*
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* Enable basic functions of the Madge chipset needed
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* for initialization.
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*/
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static void abyss_enable(struct net_device *dev)
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{
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unsigned char reset_reg;
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unsigned long ioaddr;
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ioaddr = dev->base_addr;
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reset_reg = inb(ioaddr + PCIBM2_RESET_REG);
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reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
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outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
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tms380tr_wait(100);
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}
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/*
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* Enable the functions of the Madge chipset needed for
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* full working order.
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*/
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static int abyss_chipset_init(struct net_device *dev)
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{
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unsigned char reset_reg;
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unsigned long ioaddr;
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ioaddr = dev->base_addr;
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reset_reg = inb(ioaddr + PCIBM2_RESET_REG);
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reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
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outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
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reset_reg &= ~(PCIBM2_RESET_REG_CHIP_NRES |
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PCIBM2_RESET_REG_FIFO_NRES |
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PCIBM2_RESET_REG_SIF_NRES);
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outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
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tms380tr_wait(100);
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reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
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outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
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reset_reg |= PCIBM2_RESET_REG_SIF_NRES;
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outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
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reset_reg |= PCIBM2_RESET_REG_FIFO_NRES;
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outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
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outb(PCIBM2_INT_CONTROL_REG_SINTEN |
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PCIBM2_INT_CONTROL_REG_PCI_ERR_ENABLE,
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ioaddr + PCIBM2_INT_CONTROL_REG);
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outb(30, ioaddr + PCIBM2_FIFO_THRESHOLD);
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return 0;
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}
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static inline void abyss_chipset_close(struct net_device *dev)
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{
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unsigned long ioaddr;
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ioaddr = dev->base_addr;
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outb(0, ioaddr + PCIBM2_RESET_REG);
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}
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/*
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* Read configuration data from the AT24 SEEPROM on Madge cards.
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*
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*/
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static void abyss_read_eeprom(struct net_device *dev)
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{
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struct net_local *tp;
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unsigned long ioaddr;
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unsigned short val;
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int i;
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tp = netdev_priv(dev);
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ioaddr = dev->base_addr;
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/* Must enable glue chip first */
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abyss_enable(dev);
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val = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
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PCIBM2_SEEPROM_RING_SPEED);
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tp->DataRate = val?SPEED_4:SPEED_16; /* set open speed */
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printk("%s: SEEPROM: ring speed: %dMb/sec\n", dev->name, tp->DataRate);
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val = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
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PCIBM2_SEEPROM_RAM_SIZE) * 128;
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printk("%s: SEEPROM: adapter RAM: %dkb\n", dev->name, val);
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dev->addr_len = 6;
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for (i = 0; i < 6; i++)
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dev->dev_addr[i] = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
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PCIBM2_SEEPROM_BIA+i);
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}
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static int abyss_open(struct net_device *dev)
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{
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abyss_chipset_init(dev);
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tms380tr_open(dev);
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return 0;
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}
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static int abyss_close(struct net_device *dev)
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{
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tms380tr_close(dev);
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abyss_chipset_close(dev);
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return 0;
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}
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static void __devexit abyss_detach (struct pci_dev *pdev)
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{
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struct net_device *dev = pci_get_drvdata(pdev);
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if (!dev)
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BUG();
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unregister_netdev(dev);
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release_region(dev->base_addr-0x10, ABYSS_IO_EXTENT);
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free_irq(dev->irq, dev);
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tmsdev_term(dev);
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free_netdev(dev);
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pci_set_drvdata(pdev, NULL);
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}
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static struct pci_driver abyss_driver = {
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.name = "abyss",
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.id_table = abyss_pci_tbl,
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.probe = abyss_attach,
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.remove = __devexit_p(abyss_detach),
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};
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static int __init abyss_init (void)
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{
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return pci_register_driver(&abyss_driver);
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}
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static void __exit abyss_rmmod (void)
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{
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pci_unregister_driver (&abyss_driver);
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}
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module_init(abyss_init);
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module_exit(abyss_rmmod);
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