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636 lines
19 KiB
636 lines
19 KiB
/*
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* C-Media CMI8788 driver - main driver module
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*
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* Copyright (c) Clemens Ladisch <clemens@ladisch.de>
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*
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*
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* This driver is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2.
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*
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* This driver is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this driver; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <sound/ac97_codec.h>
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#include <sound/asoundef.h>
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#include <sound/core.h>
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#include <sound/info.h>
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#include <sound/mpu401.h>
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#include <sound/pcm.h>
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#include "oxygen.h"
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#include "cm9780.h"
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MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
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MODULE_DESCRIPTION("C-Media CMI8788 helper library");
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MODULE_LICENSE("GPL v2");
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static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
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{
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struct oxygen *chip = dev_id;
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unsigned int status, clear, elapsed_streams, i;
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status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
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if (!status)
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return IRQ_NONE;
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spin_lock(&chip->reg_lock);
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clear = status & (OXYGEN_CHANNEL_A |
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OXYGEN_CHANNEL_B |
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OXYGEN_CHANNEL_C |
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OXYGEN_CHANNEL_SPDIF |
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OXYGEN_CHANNEL_MULTICH |
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OXYGEN_CHANNEL_AC97 |
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OXYGEN_INT_SPDIF_IN_DETECT |
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OXYGEN_INT_GPIO |
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OXYGEN_INT_AC97);
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if (clear) {
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if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
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chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
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oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
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chip->interrupt_mask & ~clear);
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oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
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chip->interrupt_mask);
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}
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elapsed_streams = status & chip->pcm_running;
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spin_unlock(&chip->reg_lock);
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for (i = 0; i < PCM_COUNT; ++i)
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if ((elapsed_streams & (1 << i)) && chip->streams[i])
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snd_pcm_period_elapsed(chip->streams[i]);
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if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
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spin_lock(&chip->reg_lock);
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i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
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if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
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OXYGEN_SPDIF_RATE_INT)) {
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/* write the interrupt bit(s) to clear */
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oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
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schedule_work(&chip->spdif_input_bits_work);
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}
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spin_unlock(&chip->reg_lock);
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}
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if (status & OXYGEN_INT_GPIO)
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schedule_work(&chip->gpio_work);
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if ((status & OXYGEN_INT_MIDI) && chip->midi)
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snd_mpu401_uart_interrupt(0, chip->midi->private_data);
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if (status & OXYGEN_INT_AC97)
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wake_up(&chip->ac97_waitqueue);
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return IRQ_HANDLED;
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}
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static void oxygen_spdif_input_bits_changed(struct work_struct *work)
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{
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struct oxygen *chip = container_of(work, struct oxygen,
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spdif_input_bits_work);
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u32 reg;
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/*
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* This function gets called when there is new activity on the SPDIF
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* input, or when we lose lock on the input signal, or when the rate
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* changes.
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*/
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msleep(1);
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spin_lock_irq(&chip->reg_lock);
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reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
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if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
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OXYGEN_SPDIF_LOCK_STATUS))
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== OXYGEN_SPDIF_SENSE_STATUS) {
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/*
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* If we detect activity on the SPDIF input but cannot lock to
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* a signal, the clock bit is likely to be wrong.
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*/
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reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
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oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
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spin_unlock_irq(&chip->reg_lock);
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msleep(1);
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spin_lock_irq(&chip->reg_lock);
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reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
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if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
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OXYGEN_SPDIF_LOCK_STATUS))
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== OXYGEN_SPDIF_SENSE_STATUS) {
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/* nothing detected with either clock; give up */
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if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
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== OXYGEN_SPDIF_IN_CLOCK_192) {
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/*
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* Reset clock to <= 96 kHz because this is
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* more likely to be received next time.
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*/
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reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
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reg |= OXYGEN_SPDIF_IN_CLOCK_96;
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oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
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}
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}
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}
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spin_unlock_irq(&chip->reg_lock);
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if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
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spin_lock_irq(&chip->reg_lock);
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chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
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oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
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chip->interrupt_mask);
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spin_unlock_irq(&chip->reg_lock);
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/*
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* We don't actually know that any channel status bits have
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* changed, but let's send a notification just to be sure.
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*/
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snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
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&chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
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}
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}
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static void oxygen_gpio_changed(struct work_struct *work)
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{
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struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
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if (chip->model->gpio_changed)
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chip->model->gpio_changed(chip);
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}
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#ifdef CONFIG_PROC_FS
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static void oxygen_proc_read(struct snd_info_entry *entry,
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struct snd_info_buffer *buffer)
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{
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struct oxygen *chip = entry->private_data;
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int i, j;
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snd_iprintf(buffer, "CMI8788\n\n");
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for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
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snd_iprintf(buffer, "%02x:", i);
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for (j = 0; j < 0x10; ++j)
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snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
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snd_iprintf(buffer, "\n");
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}
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if (mutex_lock_interruptible(&chip->mutex) < 0)
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return;
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if (chip->has_ac97_0) {
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snd_iprintf(buffer, "\nAC97\n");
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for (i = 0; i < 0x80; i += 0x10) {
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snd_iprintf(buffer, "%02x:", i);
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for (j = 0; j < 0x10; j += 2)
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snd_iprintf(buffer, " %04x",
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oxygen_read_ac97(chip, 0, i + j));
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snd_iprintf(buffer, "\n");
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}
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}
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if (chip->has_ac97_1) {
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snd_iprintf(buffer, "\nAC97 2\n");
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for (i = 0; i < 0x80; i += 0x10) {
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snd_iprintf(buffer, "%02x:", i);
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for (j = 0; j < 0x10; j += 2)
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snd_iprintf(buffer, " %04x",
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oxygen_read_ac97(chip, 1, i + j));
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snd_iprintf(buffer, "\n");
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}
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}
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mutex_unlock(&chip->mutex);
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}
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static void oxygen_proc_init(struct oxygen *chip)
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{
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struct snd_info_entry *entry;
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if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
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snd_info_set_text_ops(entry, chip, oxygen_proc_read);
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}
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#else
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#define oxygen_proc_init(chip)
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#endif
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static void oxygen_init(struct oxygen *chip)
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{
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unsigned int i;
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chip->dac_routing = 1;
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for (i = 0; i < 8; ++i)
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chip->dac_volume[i] = chip->model->dac_volume_min;
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chip->dac_mute = 1;
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chip->spdif_playback_enable = 1;
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chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
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(IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
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chip->spdif_pcm_bits = chip->spdif_bits;
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if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
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chip->revision = 2;
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else
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chip->revision = 1;
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if (chip->revision == 1)
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oxygen_set_bits8(chip, OXYGEN_MISC,
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OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
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i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
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chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
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chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
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oxygen_write8_masked(chip, OXYGEN_FUNCTION,
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OXYGEN_FUNCTION_RESET_CODEC |
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chip->model->function_flags,
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OXYGEN_FUNCTION_RESET_CODEC |
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OXYGEN_FUNCTION_2WIRE_SPI_MASK |
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OXYGEN_FUNCTION_ENABLE_SPI_4_5);
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oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
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oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
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oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
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OXYGEN_PLAY_CHANNELS_2 |
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OXYGEN_DMA_A_BURST_8 |
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OXYGEN_DMA_MULTICH_BURST_8);
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oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
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oxygen_write8_masked(chip, OXYGEN_MISC,
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chip->model->misc_flags,
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OXYGEN_MISC_WRITE_PCI_SUBID |
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OXYGEN_MISC_REC_C_FROM_SPDIF |
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OXYGEN_MISC_REC_B_FROM_AC97 |
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OXYGEN_MISC_REC_A_FROM_MULTICH |
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OXYGEN_MISC_MIDI);
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oxygen_write8(chip, OXYGEN_REC_FORMAT,
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(OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
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(OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
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(OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
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oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
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(OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
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(OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
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oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
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oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
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OXYGEN_RATE_48000 | chip->model->dac_i2s_format |
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OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
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OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
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if (chip->model->pcm_dev_cfg & CAPTURE_0_FROM_I2S_1)
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oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
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OXYGEN_RATE_48000 | chip->model->adc_i2s_format |
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OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
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OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
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else
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oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
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OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
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if (chip->model->pcm_dev_cfg & (CAPTURE_0_FROM_I2S_2 |
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CAPTURE_2_FROM_I2S_2))
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oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
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OXYGEN_RATE_48000 | chip->model->adc_i2s_format |
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OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
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OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
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else
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oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
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OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
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oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
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OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
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oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_OUT_ENABLE |
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OXYGEN_SPDIF_LOOPBACK);
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if (chip->model->pcm_dev_cfg & CAPTURE_1_FROM_SPDIF)
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oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_SENSE_MASK |
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OXYGEN_SPDIF_LOCK_MASK |
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OXYGEN_SPDIF_RATE_MASK |
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OXYGEN_SPDIF_LOCK_PAR |
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OXYGEN_SPDIF_IN_CLOCK_96,
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OXYGEN_SPDIF_SENSE_MASK |
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OXYGEN_SPDIF_LOCK_MASK |
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OXYGEN_SPDIF_RATE_MASK |
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OXYGEN_SPDIF_SENSE_PAR |
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OXYGEN_SPDIF_LOCK_PAR |
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OXYGEN_SPDIF_IN_CLOCK_MASK);
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else
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oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_SENSE_MASK |
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OXYGEN_SPDIF_LOCK_MASK |
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OXYGEN_SPDIF_RATE_MASK);
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oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
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oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
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OXYGEN_2WIRE_LENGTH_8 |
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OXYGEN_2WIRE_INTERRUPT_MASK |
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OXYGEN_2WIRE_SPEED_STANDARD);
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oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
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oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
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oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
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oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
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OXYGEN_PLAY_MULTICH_I2S_DAC |
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OXYGEN_PLAY_SPDIF_SPDIF |
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(0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
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(1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
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(2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
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(3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
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oxygen_write8(chip, OXYGEN_REC_ROUTING,
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OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
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OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
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OXYGEN_REC_C_ROUTE_SPDIF);
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oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
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oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
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(0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
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(1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
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(2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
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(3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
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if (chip->has_ac97_0 | chip->has_ac97_1)
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oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
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OXYGEN_AC97_INT_READ_DONE |
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OXYGEN_AC97_INT_WRITE_DONE);
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else
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oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
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oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
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oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
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if (!(chip->has_ac97_0 | chip->has_ac97_1))
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oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
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OXYGEN_AC97_CLOCK_DISABLE);
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if (!chip->has_ac97_0) {
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oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
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OXYGEN_AC97_NO_CODEC_0);
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} else {
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oxygen_write_ac97(chip, 0, AC97_RESET, 0);
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msleep(1);
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oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
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CM9780_GPIO0IO | CM9780_GPIO1IO);
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oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
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CM9780_BSTSEL | CM9780_STRO_MIC |
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CM9780_MIX2FR | CM9780_PCBSW);
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oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
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CM9780_RSOE | CM9780_CBOE |
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CM9780_SSOE | CM9780_FROE |
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CM9780_MIC2MIC | CM9780_LI2LI);
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oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
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oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
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oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
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oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
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oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
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oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
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oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
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oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
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oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
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oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
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oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
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CM9780_GPO0);
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/* power down unused ADCs and DACs */
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oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
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AC97_PD_PR0 | AC97_PD_PR1);
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oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
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AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
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}
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if (chip->has_ac97_1) {
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oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
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OXYGEN_AC97_CODEC1_SLOT3 |
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OXYGEN_AC97_CODEC1_SLOT4);
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oxygen_write_ac97(chip, 1, AC97_RESET, 0);
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msleep(1);
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oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
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oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
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oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
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oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
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oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
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|
oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
|
|
oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
|
|
oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
|
|
oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
|
|
oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
|
|
oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
|
|
oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
|
|
}
|
|
}
|
|
|
|
static void oxygen_card_free(struct snd_card *card)
|
|
{
|
|
struct oxygen *chip = card->private_data;
|
|
|
|
spin_lock_irq(&chip->reg_lock);
|
|
chip->interrupt_mask = 0;
|
|
chip->pcm_running = 0;
|
|
oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
|
|
oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
if (chip->irq >= 0)
|
|
free_irq(chip->irq, chip);
|
|
flush_scheduled_work();
|
|
chip->model->cleanup(chip);
|
|
mutex_destroy(&chip->mutex);
|
|
pci_release_regions(chip->pci);
|
|
pci_disable_device(chip->pci);
|
|
}
|
|
|
|
int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
|
|
const struct oxygen_model *model)
|
|
{
|
|
struct snd_card *card;
|
|
struct oxygen *chip;
|
|
int err;
|
|
|
|
card = snd_card_new(index, id, model->owner,
|
|
sizeof *chip + model->model_data_size);
|
|
if (!card)
|
|
return -ENOMEM;
|
|
|
|
chip = card->private_data;
|
|
chip->card = card;
|
|
chip->pci = pci;
|
|
chip->irq = -1;
|
|
chip->model = model;
|
|
chip->model_data = chip + 1;
|
|
spin_lock_init(&chip->reg_lock);
|
|
mutex_init(&chip->mutex);
|
|
INIT_WORK(&chip->spdif_input_bits_work,
|
|
oxygen_spdif_input_bits_changed);
|
|
INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
|
|
init_waitqueue_head(&chip->ac97_waitqueue);
|
|
|
|
err = pci_enable_device(pci);
|
|
if (err < 0)
|
|
goto err_card;
|
|
|
|
err = pci_request_regions(pci, model->chip);
|
|
if (err < 0) {
|
|
snd_printk(KERN_ERR "cannot reserve PCI resources\n");
|
|
goto err_pci_enable;
|
|
}
|
|
|
|
if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
|
|
pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
|
|
snd_printk(KERN_ERR "invalid PCI I/O range\n");
|
|
err = -ENXIO;
|
|
goto err_pci_regions;
|
|
}
|
|
chip->addr = pci_resource_start(pci, 0);
|
|
|
|
pci_set_master(pci);
|
|
snd_card_set_dev(card, &pci->dev);
|
|
card->private_free = oxygen_card_free;
|
|
|
|
oxygen_init(chip);
|
|
model->init(chip);
|
|
|
|
err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
|
|
model->chip, chip);
|
|
if (err < 0) {
|
|
snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
|
|
goto err_card;
|
|
}
|
|
chip->irq = pci->irq;
|
|
|
|
strcpy(card->driver, model->chip);
|
|
strcpy(card->shortname, model->shortname);
|
|
sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
|
|
model->longname, chip->revision, chip->addr, chip->irq);
|
|
strcpy(card->mixername, model->chip);
|
|
snd_component_add(card, model->chip);
|
|
|
|
err = oxygen_pcm_init(chip);
|
|
if (err < 0)
|
|
goto err_card;
|
|
|
|
err = oxygen_mixer_init(chip);
|
|
if (err < 0)
|
|
goto err_card;
|
|
|
|
if (model->misc_flags & OXYGEN_MISC_MIDI) {
|
|
err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
|
|
chip->addr + OXYGEN_MPU401,
|
|
MPU401_INFO_INTEGRATED, 0, 0,
|
|
&chip->midi);
|
|
if (err < 0)
|
|
goto err_card;
|
|
}
|
|
|
|
oxygen_proc_init(chip);
|
|
|
|
spin_lock_irq(&chip->reg_lock);
|
|
if (chip->model->pcm_dev_cfg & CAPTURE_1_FROM_SPDIF)
|
|
chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
|
|
if (chip->has_ac97_0 | chip->has_ac97_1)
|
|
chip->interrupt_mask |= OXYGEN_INT_AC97;
|
|
oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
|
|
err = snd_card_register(card);
|
|
if (err < 0)
|
|
goto err_card;
|
|
|
|
pci_set_drvdata(pci, card);
|
|
return 0;
|
|
|
|
err_pci_regions:
|
|
pci_release_regions(pci);
|
|
err_pci_enable:
|
|
pci_disable_device(pci);
|
|
err_card:
|
|
snd_card_free(card);
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL(oxygen_pci_probe);
|
|
|
|
void oxygen_pci_remove(struct pci_dev *pci)
|
|
{
|
|
snd_card_free(pci_get_drvdata(pci));
|
|
pci_set_drvdata(pci, NULL);
|
|
}
|
|
EXPORT_SYMBOL(oxygen_pci_remove);
|
|
|
|
#ifdef CONFIG_PM
|
|
int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state)
|
|
{
|
|
struct snd_card *card = pci_get_drvdata(pci);
|
|
struct oxygen *chip = card->private_data;
|
|
unsigned int i, saved_interrupt_mask;
|
|
|
|
snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
|
|
|
|
for (i = 0; i < PCM_COUNT; ++i)
|
|
if (chip->streams[i])
|
|
snd_pcm_suspend(chip->streams[i]);
|
|
|
|
if (chip->model->suspend)
|
|
chip->model->suspend(chip);
|
|
|
|
spin_lock_irq(&chip->reg_lock);
|
|
saved_interrupt_mask = chip->interrupt_mask;
|
|
chip->interrupt_mask = 0;
|
|
oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
|
|
oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
|
|
synchronize_irq(chip->irq);
|
|
flush_scheduled_work();
|
|
chip->interrupt_mask = saved_interrupt_mask;
|
|
|
|
pci_disable_device(pci);
|
|
pci_save_state(pci);
|
|
pci_set_power_state(pci, pci_choose_state(pci, state));
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(oxygen_pci_suspend);
|
|
|
|
static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
|
|
0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
|
|
0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
|
|
};
|
|
static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
|
|
{ 0x18284fa2, 0x03060000 },
|
|
{ 0x00007fa6, 0x00200000 }
|
|
};
|
|
|
|
static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
|
|
{
|
|
return bitmap[bit / 32] & (1 << (bit & 31));
|
|
}
|
|
|
|
static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
|
|
{
|
|
unsigned int i;
|
|
|
|
oxygen_write_ac97(chip, codec, AC97_RESET, 0);
|
|
msleep(1);
|
|
for (i = 1; i < 0x40; ++i)
|
|
if (is_bit_set(ac97_registers_to_restore[codec], i))
|
|
oxygen_write_ac97(chip, codec, i * 2,
|
|
chip->saved_ac97_registers[codec][i]);
|
|
}
|
|
|
|
int oxygen_pci_resume(struct pci_dev *pci)
|
|
{
|
|
struct snd_card *card = pci_get_drvdata(pci);
|
|
struct oxygen *chip = card->private_data;
|
|
unsigned int i;
|
|
|
|
pci_set_power_state(pci, PCI_D0);
|
|
pci_restore_state(pci);
|
|
if (pci_enable_device(pci) < 0) {
|
|
snd_printk(KERN_ERR "cannot reenable device");
|
|
snd_card_disconnect(card);
|
|
return -EIO;
|
|
}
|
|
pci_set_master(pci);
|
|
|
|
oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
|
|
oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
|
|
for (i = 0; i < OXYGEN_IO_SIZE; ++i)
|
|
if (is_bit_set(registers_to_restore, i))
|
|
oxygen_write8(chip, i, chip->saved_registers._8[i]);
|
|
if (chip->has_ac97_0)
|
|
oxygen_restore_ac97(chip, 0);
|
|
if (chip->has_ac97_1)
|
|
oxygen_restore_ac97(chip, 1);
|
|
|
|
if (chip->model->resume)
|
|
chip->model->resume(chip);
|
|
|
|
oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
|
|
|
|
snd_power_change_state(card, SNDRV_CTL_POWER_D0);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(oxygen_pci_resume);
|
|
#endif /* CONFIG_PM */
|
|
|