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309 lines
7.6 KiB
309 lines
7.6 KiB
/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MSM_CLOCK_GENERIC_H
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#define __MSM_CLOCK_GENERIC_H
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#include <linux/clk/msm-clk-provider.h>
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#include <linux/of.h>
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/**
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* struct fixed_clk - fixed rate clock
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* @c: clk
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*/
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struct fixed_clk {
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struct clk c;
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};
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/* ==================== Mux clock ==================== */
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struct mux_clk;
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struct clk_mux_ops {
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int (*set_mux_sel)(struct mux_clk *clk, int sel);
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int (*get_mux_sel)(struct mux_clk *clk);
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/* Optional */
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bool (*is_enabled)(struct mux_clk *clk);
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int (*enable)(struct mux_clk *clk);
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void (*disable)(struct mux_clk *clk);
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void __iomem *(*list_registers)(struct mux_clk *clk, int n,
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struct clk_register_data **regs, u32 *size);
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};
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#define MUX_SRC_LIST(...) \
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.parents = (struct clk_src[]){__VA_ARGS__}, \
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.num_parents = ARRAY_SIZE(((struct clk_src[]){__VA_ARGS__}))
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#define MUX_REC_SRC_LIST(...) \
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.rec_parents = (struct clk * []){__VA_ARGS__}, \
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.num_rec_parents = ARRAY_SIZE(((struct clk * []){__VA_ARGS__}))
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struct mux_clk {
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/* Parents in decreasing order of preference for obtaining rates. */
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struct clk_src *parents;
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int num_parents;
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/* Recursively search for the requested parent in rec_parents. */
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struct clk **rec_parents;
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int num_rec_parents;
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struct clk *safe_parent;
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int safe_sel;
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unsigned long safe_freq;
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/*
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* Before attempting a clk_round_rate on available sources, attempt a
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* clk_get_rate on all those sources. If one of them is already at the
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* necessary rate, that source will be used.
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*/
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bool try_get_rate;
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struct clk_mux_ops *ops;
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/*
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* Set if you need the mux to try a new parent before falling back to
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* the current parent. If the safe_parent field above is set, then the
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* safe_sel intermediate source will only be used if we fall back to
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* to the current parent during mux_set_rate.
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*/
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bool try_new_parent;
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/* Fields not used by helper function. */
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void *const __iomem *base;
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u32 offset;
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u32 en_offset;
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u32 mask;
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u32 shift;
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u32 en_mask;
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/*
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* Set post divider for debug mux in order to divide the clock
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* by post_div + 1.
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*/
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u32 post_div;
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int low_power_sel;
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void *priv;
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struct clk c;
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};
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static inline struct mux_clk *to_mux_clk(struct clk *c)
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{
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return container_of(c, struct mux_clk, c);
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}
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extern const struct clk_ops clk_ops_gen_mux;
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/* ==================== Divider clock ==================== */
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struct div_clk;
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struct clk_div_ops {
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int (*set_div)(struct div_clk *clk, int div);
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int (*get_div)(struct div_clk *clk);
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bool (*is_enabled)(struct div_clk *clk);
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int (*enable)(struct div_clk *clk);
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void (*disable)(struct div_clk *clk);
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void __iomem *(*list_registers)(struct div_clk *clk, int n,
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struct clk_register_data **regs, u32 *size);
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};
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struct div_data {
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unsigned int div;
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unsigned int min_div;
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unsigned int max_div;
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unsigned long rate_margin;
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/*
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* Indicate whether this divider clock supports half-integer divider.
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* If it is, all the min_div and max_div have been doubled. It means
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* they are 2*N.
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*/
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bool is_half_divider;
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/*
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* Skip odd dividers since the hardware may not support them.
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*/
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bool skip_odd_div;
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bool skip_even_div;
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bool allow_div_one;
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unsigned int cached_div;
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};
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struct div_clk {
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struct div_data data;
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/*
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* Some implementations may require the divider to be set to a "safe"
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* value that allows reprogramming of upstream clocks without violating
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* voltage constraints.
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*/
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unsigned long safe_freq;
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/* Optional */
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struct clk_div_ops *ops;
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/* Fields not used by helper function. */
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void *const __iomem *base;
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u32 offset;
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u32 mask;
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u32 shift;
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u32 en_mask;
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void *priv;
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struct clk c;
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};
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static inline struct div_clk *to_div_clk(struct clk *c)
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{
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return container_of(c, struct div_clk, c);
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}
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extern const struct clk_ops clk_ops_div;
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extern const struct clk_ops clk_ops_slave_div;
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struct ext_clk {
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struct clk c;
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struct device *dev;
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char *clk_id;
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};
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long parent_round_rate(struct clk *c, unsigned long rate);
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unsigned long parent_get_rate(struct clk *c);
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int parent_set_rate(struct clk *c, unsigned long rate);
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static inline struct ext_clk *to_ext_clk(struct clk *c)
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{
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return container_of(c, struct ext_clk, c);
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}
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extern const struct clk_ops clk_ops_ext;
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#define DEFINE_FIXED_DIV_CLK(clk_name, _div, _parent) \
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static struct div_clk clk_name = { \
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.data = { \
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.max_div = _div, \
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.min_div = _div, \
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.div = _div, \
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}, \
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.c = { \
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.parent = _parent, \
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.dbg_name = #clk_name, \
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.ops = &clk_ops_div, \
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CLK_INIT(clk_name.c), \
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} \
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}
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#define DEFINE_FIXED_SLAVE_DIV_CLK(clk_name, _div, _parent) \
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static struct div_clk clk_name = { \
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.data = { \
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.max_div = _div, \
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.min_div = _div, \
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.div = _div, \
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}, \
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.c = { \
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.parent = _parent, \
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.dbg_name = #clk_name, \
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.ops = &clk_ops_slave_div, \
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CLK_INIT(clk_name.c), \
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} \
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}
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#define DEFINE_EXT_CLK(clk_name, _parent) \
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static struct ext_clk clk_name = { \
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.c = { \
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.parent = _parent, \
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.dbg_name = #clk_name, \
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.ops = &clk_ops_ext, \
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CLK_INIT(clk_name.c), \
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} \
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}
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/* ==================== Mux Div clock ==================== */
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struct mux_div_clk;
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/*
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* struct mux_div_ops
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* the enable and disable ops are optional.
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*/
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struct mux_div_ops {
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int (*set_src_div)(struct mux_div_clk *, u32 src_sel, u32 div);
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void (*get_src_div)(struct mux_div_clk *, u32 *src_sel, u32 *div);
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int (*enable)(struct mux_div_clk *);
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void (*disable)(struct mux_div_clk *);
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bool (*is_enabled)(struct mux_div_clk *);
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void __iomem *(*list_registers)(struct mux_div_clk *md, int n,
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struct clk_register_data **regs, u32 *size);
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};
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/*
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* struct mux_div_clk - combined mux/divider clock
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* @priv
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parameters needed by ops
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* @safe_freq
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when switching rates from A to B, the mux div clock will
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instead switch from A -> safe_freq -> B. This allows the
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mux_div clock to change rates while enabled, even if this
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behavior is not supported by the parent clocks.
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If changing the rate of parent A also causes the rate of
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parent B to change, then safe_freq must be defined.
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safe_freq is expected to have a source clock which is always
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on and runs at only one rate.
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* @parents
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list of parents and mux indicies
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* @ops
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function pointers for hw specific operations
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* @src_sel
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the mux index which will be used if the clock is enabled.
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* @try_get_rate
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Set if you need the mux to directly jump to a source
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that is at the desired rate currently.
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* @force_enable_md
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Set if the mux-div needs to be force enabled/disabled during
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clk_enable/disable.
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*/
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struct mux_div_clk {
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/* Required parameters */
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struct mux_div_ops *ops;
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struct div_data data;
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struct clk_src *parents;
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u32 num_parents;
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struct clk c;
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/* Internal */
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u32 src_sel;
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/* Optional parameters */
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void *priv;
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void __iomem *base;
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u32 div_mask;
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u32 div_offset;
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u32 div_shift;
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u32 src_mask;
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u32 src_offset;
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u32 src_shift;
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u32 en_mask;
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u32 en_offset;
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u32 safe_div;
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struct clk *safe_parent;
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unsigned long safe_freq;
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bool try_get_rate;
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bool force_enable_md;
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};
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static inline struct mux_div_clk *to_mux_div_clk(struct clk *clk)
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{
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return container_of(clk, struct mux_div_clk, c);
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}
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extern const struct clk_ops clk_ops_mux_div_clk;
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#endif
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