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736 lines
17 KiB
736 lines
17 KiB
/* Copyright (c) 2010-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include <linux/tick.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include<linux/ktime.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/spinlock.h>
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#include <linux/of_irq.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/cpu_pm.h>
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#include <asm/arch_timer.h>
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#include <soc/qcom/rpm-notifier.h>
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#include <soc/qcom/lpm_levels.h>
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#include "mpm.h"
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#define CREATE_TRACE_POINTS
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#include "trace/events/mpm.h"
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#define ARCH_TIMER_HZ (19200000)
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#define MAX_MPM_PIN_PER_IRQ 2
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#define CLEAR_INTR(reg, intr) (reg & ~(1 << intr))
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#define ENABLE_INTR(reg, intr) (reg | (1 << intr))
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#define CLEAR_TYPE(reg, type) (reg & ~(1 << type))
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#define ENABLE_TYPE(reg, type) (reg | (1 << type))
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#define MPM_REG_ENABLE 0
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#define MPM_REG_FALLING_EDGE 1
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#define MPM_REG_RISING_EDGE 2
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#define MPM_REG_POLARITY 3
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#define MPM_REG_STATUS 4
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#define QCOM_MPM_REG_WIDTH DIV_ROUND_UP(num_mpm_irqs, 32)
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#define MPM_REGISTER(reg, index) ((reg * QCOM_MPM_REG_WIDTH + index + 2) * (4))
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struct msm_mpm_device_data {
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struct device *dev;
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void __iomem *mpm_request_reg_base;
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void __iomem *mpm_ipc_reg;
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irq_hw_number_t ipc_irq;
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struct irq_domain *gic_chip_domain;
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struct irq_domain *gpio_chip_domain;
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};
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static int msm_pm_sleep_time_override;
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static int num_mpm_irqs = 64;
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module_param_named(sleep_time_override,
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msm_pm_sleep_time_override, int, 0664);
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static struct msm_mpm_device_data msm_mpm_dev_data;
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static unsigned int *mpm_to_irq;
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static DEFINE_SPINLOCK(mpm_lock);
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static int msm_get_irq_pin(int mpm_pin, struct mpm_pin *mpm_data)
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{
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int i = 0;
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if (!mpm_data)
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return -ENODEV;
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for (i = 0; mpm_data[i].pin >= 0; i++) {
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if (mpm_data[i].pin == mpm_pin)
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return mpm_to_irq[mpm_data[i].pin];
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}
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return -EINVAL;
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}
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static void msm_get_mpm_pin(struct irq_data *d, int *mpm_pin)
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{
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struct mpm_pin *mpm_data = NULL;
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int i = 0, j = 0;
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if (!d || !d->domain->host_data)
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return;
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mpm_data = d->domain->host_data;
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for (i = 0; (mpm_data[i].pin >= 0) && (j < MAX_MPM_PIN_PER_IRQ); i++) {
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if (mpm_data[i].hwirq == d->hwirq) {
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mpm_pin[j] = mpm_data[i].pin;
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mpm_to_irq[mpm_data[i].pin] = d->irq;
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j++;
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}
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}
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}
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static inline uint32_t msm_mpm_read(unsigned int reg, unsigned int subreg_index)
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{
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unsigned int offset = MPM_REGISTER(reg, subreg_index);
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return readl_relaxed(msm_mpm_dev_data.mpm_request_reg_base + offset);
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}
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static inline void msm_mpm_write(unsigned int reg,
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unsigned int subreg_index,
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uint32_t value)
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{
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void __iomem *mpm_reg_base = msm_mpm_dev_data.mpm_request_reg_base;
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/*
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* Add 2 to offset to account for the 64 bit timer in the vMPM
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* mapping
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*/
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unsigned int offset = MPM_REGISTER(reg, subreg_index);
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u32 r_value;
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writel_relaxed(value, mpm_reg_base + offset);
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do {
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r_value = readl_relaxed(mpm_reg_base + offset);
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udelay(5);
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} while (r_value != value);
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}
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static inline void msm_mpm_enable_irq(struct irq_data *d, bool on)
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{
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int mpm_pin[MAX_MPM_PIN_PER_IRQ] = {-1, -1};
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unsigned long flags;
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int i = 0;
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u32 enable;
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unsigned int index, mask;
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unsigned int reg;
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reg = MPM_REG_ENABLE;
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msm_get_mpm_pin(d, mpm_pin);
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for (i = 0; i < MAX_MPM_PIN_PER_IRQ; i++) {
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if (mpm_pin[i] < 0)
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return;
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index = mpm_pin[i]/32;
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mask = mpm_pin[i]%32;
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spin_lock_irqsave(&mpm_lock, flags);
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enable = msm_mpm_read(reg, index);
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if (on)
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enable = ENABLE_INTR(enable, mask);
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else
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enable = CLEAR_INTR(enable, mask);
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msm_mpm_write(reg, index, enable);
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spin_unlock_irqrestore(&mpm_lock, flags);
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}
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}
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static void msm_mpm_program_set_type(bool set, unsigned int reg,
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unsigned int index, unsigned int mask)
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{
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u32 type;
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type = msm_mpm_read(reg, index);
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if (set)
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type = ENABLE_TYPE(type, mask);
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else
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type = CLEAR_TYPE(type, mask);
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msm_mpm_write(reg, index, type);
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}
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static void msm_mpm_set_type(struct irq_data *d,
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unsigned int flowtype)
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{
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int mpm_pin[MAX_MPM_PIN_PER_IRQ] = {-1, -1};
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unsigned long flags;
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int i = 0;
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unsigned int index, mask;
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unsigned int reg = 0;
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msm_get_mpm_pin(d, mpm_pin);
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for (i = 0; i < MAX_MPM_PIN_PER_IRQ; i++) {
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if (mpm_pin[i] < 0)
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return;
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index = mpm_pin[i]/32;
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mask = mpm_pin[i]%32;
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spin_lock_irqsave(&mpm_lock, flags);
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reg = MPM_REG_RISING_EDGE;
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if (flowtype & IRQ_TYPE_EDGE_RISING)
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msm_mpm_program_set_type(1, reg, index, mask);
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else
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msm_mpm_program_set_type(0, reg, index, mask);
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reg = MPM_REG_FALLING_EDGE;
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if (flowtype & IRQ_TYPE_EDGE_FALLING)
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msm_mpm_program_set_type(1, reg, index, mask);
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else
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msm_mpm_program_set_type(0, reg, index, mask);
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reg = MPM_REG_POLARITY;
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if (flowtype & IRQ_TYPE_LEVEL_HIGH)
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msm_mpm_program_set_type(1, reg, index, mask);
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else
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msm_mpm_program_set_type(0, reg, index, mask);
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spin_unlock_irqrestore(&mpm_lock, flags);
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}
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}
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static void msm_mpm_gpio_chip_mask(struct irq_data *d)
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{
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msm_mpm_enable_irq(d, false);
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}
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static void msm_mpm_gpio_chip_unmask(struct irq_data *d)
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{
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msm_mpm_enable_irq(d, true);
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}
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static int msm_mpm_gpio_chip_set_type(struct irq_data *d, unsigned int type)
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{
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msm_mpm_set_type(d, type);
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return 0;
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}
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static void msm_mpm_gic_chip_mask(struct irq_data *d)
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{
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msm_mpm_enable_irq(d, false);
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irq_chip_mask_parent(d);
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}
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static void msm_mpm_gic_chip_unmask(struct irq_data *d)
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{
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msm_mpm_enable_irq(d, true);
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irq_chip_unmask_parent(d);
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}
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static int msm_mpm_gic_chip_set_type(struct irq_data *d, unsigned int type)
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{
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msm_mpm_set_type(d, type);
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return irq_chip_set_type_parent(d, type);
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}
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static struct irq_chip msm_mpm_gic_chip = {
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.name = "mpm-gic",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = msm_mpm_gic_chip_mask,
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.irq_disable = msm_mpm_gic_chip_mask,
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.irq_unmask = msm_mpm_gic_chip_unmask,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_wake = irq_chip_set_wake_parent,
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.irq_set_type = msm_mpm_gic_chip_set_type,
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.flags = IRQCHIP_MASK_ON_SUSPEND,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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};
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static struct irq_chip msm_mpm_gpio_chip = {
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.name = "mpm-gpio",
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.irq_mask = msm_mpm_gpio_chip_mask,
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.irq_disable = msm_mpm_gpio_chip_mask,
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.irq_unmask = msm_mpm_gpio_chip_unmask,
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.irq_set_type = msm_mpm_gpio_chip_set_type,
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.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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};
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static int msm_mpm_gpio_chip_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 2)
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return -EINVAL;
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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return 0;
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}
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return -EINVAL;
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}
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static int msm_mpm_gpio_chip_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs,
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void *data)
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{
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int ret = 0;
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struct irq_fwspec *fwspec = data;
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irq_hw_number_t hwirq;
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unsigned int type = IRQ_TYPE_NONE;
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ret = msm_mpm_gpio_chip_translate(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&msm_mpm_gpio_chip, NULL);
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return 0;
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}
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static const struct irq_domain_ops msm_mpm_gpio_chip_domain_ops = {
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.translate = msm_mpm_gpio_chip_translate,
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.alloc = msm_mpm_gpio_chip_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int msm_mpm_gic_chip_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count < 3)
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return -EINVAL;
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switch (fwspec->param[0]) {
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case 0: /* SPI */
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*hwirq = fwspec->param[1] + 32;
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break;
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case 1: /* PPI */
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*hwirq = fwspec->param[1] + 16;
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break;
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case GIC_IRQ_TYPE_LPI: /* LPI */
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*hwirq = fwspec->param[1];
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break;
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default:
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return -EINVAL;
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}
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*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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if (is_fwnode_irqchip(fwspec->fwnode)) {
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if (fwspec->param_count != 2)
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return -EINVAL;
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*hwirq = fwspec->param[0];
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*type = fwspec->param[1];
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return 0;
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}
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return -EINVAL;
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}
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static int msm_mpm_gic_chip_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs,
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void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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unsigned int type;
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int ret;
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ret = msm_mpm_gic_chip_translate(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&msm_mpm_gic_chip, NULL);
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = domain->parent->fwnode;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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}
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static const struct irq_domain_ops msm_mpm_gic_chip_domain_ops = {
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.translate = msm_mpm_gic_chip_translate,
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.alloc = msm_mpm_gic_chip_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static inline void msm_mpm_send_interrupt(void)
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{
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writel_relaxed(2, msm_mpm_dev_data.mpm_ipc_reg);
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/* Ensure the write is complete before returning. */
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wmb();
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}
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static inline void msm_mpm_timer_write(uint32_t *expiry)
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{
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writel_relaxed(expiry[0], msm_mpm_dev_data.mpm_request_reg_base);
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writel_relaxed(expiry[1], msm_mpm_dev_data.mpm_request_reg_base + 0x4);
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}
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static void msm_mpm_enter_sleep(struct cpumask *cpumask)
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{
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msm_mpm_send_interrupt();
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irq_set_affinity(msm_mpm_dev_data.ipc_irq, cpumask);
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}
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static int msm_get_apps_irq(unsigned int mpm_irq)
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{
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struct mpm_pin *mpm_pin = NULL;
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int apps_irq;
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mpm_pin = (struct mpm_pin *)
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msm_mpm_dev_data.gic_chip_domain->host_data;
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apps_irq = msm_get_irq_pin(mpm_irq, mpm_pin);
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if (apps_irq >= 0)
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return apps_irq;
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mpm_pin = (struct mpm_pin *)
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msm_mpm_dev_data.gpio_chip_domain->host_data;
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return msm_get_irq_pin(mpm_irq, mpm_pin);
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}
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static void system_pm_exit_sleep(bool success)
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{
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msm_rpm_exit_sleep();
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}
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static u64 us_to_ticks(uint64_t sleep_val)
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{
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uint64_t sec, nsec;
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u64 wakeup;
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sec = sleep_val;
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do_div(sec, USEC_PER_SEC);
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nsec = sleep_val - sec * USEC_PER_SEC;
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if (nsec > 0) {
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nsec = nsec * NSEC_PER_USEC;
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do_div(nsec, NSEC_PER_SEC);
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}
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sleep_val = sec + nsec;
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wakeup = (u64)sleep_val * ARCH_TIMER_HZ;
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if (sleep_val)
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wakeup += arch_counter_get_cntvct();
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else
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wakeup = (~0ULL);
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return wakeup;
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}
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static int system_pm_update_wakeup(bool from_idle)
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{
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uint64_t wake_time;
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uint32_t lo = ~0U, hi = ~0U;
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u64 wakeup;
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if (unlikely(!from_idle && msm_pm_sleep_time_override)) {
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wake_time = msm_pm_sleep_time_override * USEC_PER_SEC;
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wakeup = us_to_ticks(wake_time);
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} else {
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/* Read the hardware to get the most accurate value */
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arch_timer_mem_get_cval(&lo, &hi);
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wakeup = lo;
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wakeup |= ((uint64_t)(hi) << 32);
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}
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msm_mpm_timer_write((uint32_t *)&wakeup);
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trace_mpm_wakeup_time(from_idle, wakeup, arch_counter_get_cntvct());
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return 0;
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}
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static int system_pm_enter_sleep(struct cpumask *mask)
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{
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int ret = 0;
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ret = msm_rpm_enter_sleep(0, mask);
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if (ret)
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return ret;
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msm_mpm_enter_sleep(mask);
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return ret;
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}
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static bool system_pm_sleep_allowed(void)
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{
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return !msm_rpm_waiting_for_ack();
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}
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|
|
static struct system_pm_ops pm_ops = {
|
|
.enter = system_pm_enter_sleep,
|
|
.exit = system_pm_exit_sleep,
|
|
.update_wakeup = system_pm_update_wakeup,
|
|
.sleep_allowed = system_pm_sleep_allowed,
|
|
};
|
|
|
|
/*
|
|
* Triggered by RPM when system resumes from deep sleep
|
|
*/
|
|
static irqreturn_t msm_mpm_irq(int irq, void *dev_id)
|
|
{
|
|
unsigned long pending;
|
|
uint32_t value[3];
|
|
int i, k, apps_irq;
|
|
unsigned int mpm_irq;
|
|
struct irq_desc *desc = NULL;
|
|
unsigned int reg = MPM_REG_ENABLE;
|
|
|
|
for (i = 0; i < QCOM_MPM_REG_WIDTH; i++) {
|
|
value[i] = msm_mpm_read(reg, i);
|
|
trace_mpm_wakeup_enable_irqs(i, value[i]);
|
|
}
|
|
|
|
for (i = 0; i < QCOM_MPM_REG_WIDTH; i++) {
|
|
pending = msm_mpm_read(MPM_REG_STATUS, i);
|
|
pending &= (unsigned long)value[i];
|
|
|
|
trace_mpm_wakeup_pending_irqs(i, pending);
|
|
for_each_set_bit(k, &pending, 32) {
|
|
mpm_irq = 32 * i + k;
|
|
apps_irq = msm_get_apps_irq(mpm_irq);
|
|
desc = apps_irq ?
|
|
irq_to_desc(apps_irq) : NULL;
|
|
|
|
if (desc && !irqd_is_level_type(&desc->irq_data))
|
|
irq_set_irqchip_state(apps_irq,
|
|
IRQCHIP_STATE_PENDING, true);
|
|
|
|
}
|
|
|
|
msm_mpm_write(MPM_REG_STATUS, i, 0);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int msm_mpm_init(struct device_node *node)
|
|
{
|
|
struct msm_mpm_device_data *dev = &msm_mpm_dev_data;
|
|
int ret = 0;
|
|
int irq, index;
|
|
|
|
index = of_property_match_string(node, "reg-names", "vmpm");
|
|
if (index < 0) {
|
|
ret = -EADDRNOTAVAIL;
|
|
goto reg_base_err;
|
|
}
|
|
|
|
dev->mpm_request_reg_base = of_iomap(node, index);
|
|
if (!dev->mpm_request_reg_base) {
|
|
pr_err("Unable to iomap\n");
|
|
ret = -EADDRNOTAVAIL;
|
|
goto reg_base_err;
|
|
}
|
|
|
|
index = of_property_match_string(node, "reg-names", "ipc");
|
|
if (index < 0) {
|
|
ret = -EADDRNOTAVAIL;
|
|
goto reg_base_err;
|
|
}
|
|
|
|
dev->mpm_ipc_reg = of_iomap(node, index);
|
|
if (!dev->mpm_ipc_reg) {
|
|
pr_err("Unable to iomap IPC register\n");
|
|
ret = -EADDRNOTAVAIL;
|
|
goto ipc_reg_err;
|
|
}
|
|
|
|
irq = of_irq_get(node, 0);
|
|
if (irq <= 0) {
|
|
pr_err("no IRQ resource info\n");
|
|
ret = irq;
|
|
goto ipc_irq_err;
|
|
}
|
|
dev->ipc_irq = irq;
|
|
|
|
ret = request_irq(dev->ipc_irq, msm_mpm_irq,
|
|
IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "mpm",
|
|
msm_mpm_irq);
|
|
if (ret) {
|
|
pr_err("request_irq failed errno: %d\n", ret);
|
|
goto ipc_irq_err;
|
|
}
|
|
|
|
ret = irq_set_irq_wake(dev->ipc_irq, 1);
|
|
if (ret) {
|
|
pr_err("failed to set wakeup irq %lu: %d\n",
|
|
dev->ipc_irq, ret);
|
|
goto set_wake_irq_err;
|
|
}
|
|
|
|
return register_system_pm_ops(&pm_ops);
|
|
|
|
set_wake_irq_err:
|
|
free_irq(dev->ipc_irq, msm_mpm_irq);
|
|
ipc_irq_err:
|
|
iounmap(dev->mpm_ipc_reg);
|
|
ipc_reg_err:
|
|
iounmap(dev->mpm_request_reg_base);
|
|
reg_base_err:
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id mpm_gic_chip_data_table[] = {
|
|
{
|
|
.compatible = "qcom,mpm-gic-mdm9607",
|
|
.data = mpm_mdm9607_gic_chip_data,
|
|
},
|
|
{
|
|
.compatible = "qcom,mpm-gic-msm8937",
|
|
.data = mpm_msm8937_gic_chip_data,
|
|
},
|
|
{
|
|
.compatible = "qcom,mpm-gic-qcs405",
|
|
.data = mpm_qcs405_gic_chip_data,
|
|
},
|
|
{
|
|
.compatible = "qcom,mpm-gic-trinket",
|
|
.data = mpm_trinket_gic_chip_data,
|
|
},
|
|
{
|
|
.compatible = "qcom,mpm-gic-sdm660",
|
|
.data = mpm_sdm660_gic_chip_data,
|
|
},
|
|
{
|
|
.compatible = "qcom,mpm-gic-sdm429",
|
|
.data = mpm_sdm429_gic_chip_data,
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mpm_gic_chip_data_table);
|
|
|
|
static const struct of_device_id mpm_gpio_chip_data_table[] = {
|
|
{
|
|
.compatible = "qcom,mpm-gpio-mdm9607",
|
|
.data = mpm_mdm9607_gpio_chip_data,
|
|
},
|
|
{
|
|
.compatible = "qcom,mpm-gpio-msm8937",
|
|
.data = mpm_msm8937_gpio_chip_data,
|
|
},
|
|
{
|
|
.compatible = "qcom,mpm-gpio-qcs405",
|
|
.data = mpm_qcs405_gpio_chip_data,
|
|
},
|
|
{
|
|
.compatible = "qcom,mpm-gpio-trinket",
|
|
.data = mpm_trinket_gpio_chip_data,
|
|
},
|
|
{
|
|
.compatible = "qcom,mpm-gpio-sdm660",
|
|
.data = mpm_sdm660_gpio_chip_data,
|
|
},
|
|
{
|
|
.compatible = "qcom,mpm-gpio-sdm429",
|
|
.data = mpm_sdm429_gpio_chip_data,
|
|
},
|
|
{}
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mpm_gpio_chip_data_table);
|
|
|
|
static int __init mpm_gic_chip_init(struct device_node *node,
|
|
struct device_node *parent)
|
|
{
|
|
struct irq_domain *parent_domain;
|
|
const struct of_device_id *id;
|
|
int ret;
|
|
|
|
if (!parent) {
|
|
pr_err("%s(): no parent for mpm-gic\n", node->full_name);
|
|
return -ENXIO;
|
|
}
|
|
|
|
parent_domain = irq_find_host(parent);
|
|
if (!parent_domain) {
|
|
pr_err("unable to obtain gic parent domain\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
of_property_read_u32(node, "qcom,num-mpm-irqs", &num_mpm_irqs);
|
|
|
|
mpm_to_irq = kcalloc(num_mpm_irqs, sizeof(*mpm_to_irq), GFP_KERNEL);
|
|
if (!mpm_to_irq)
|
|
return -ENOMEM;
|
|
|
|
id = of_match_node(mpm_gic_chip_data_table, node);
|
|
if (!id) {
|
|
pr_err("can not find mpm_gic_data_table of_node\n");
|
|
ret = -ENODEV;
|
|
goto mpm_map_err;
|
|
}
|
|
|
|
msm_mpm_dev_data.gic_chip_domain = irq_domain_add_hierarchy(
|
|
parent_domain, 0, num_mpm_irqs, node,
|
|
&msm_mpm_gic_chip_domain_ops, (void *)id->data);
|
|
if (!msm_mpm_dev_data.gic_chip_domain) {
|
|
pr_err("gic domain add failed\n");
|
|
ret = -ENOMEM;
|
|
goto mpm_map_err;
|
|
}
|
|
|
|
ret = msm_mpm_init(node);
|
|
if (!ret)
|
|
return ret;
|
|
irq_domain_remove(msm_mpm_dev_data.gic_chip_domain);
|
|
|
|
mpm_map_err:
|
|
kfree(mpm_to_irq);
|
|
return ret;
|
|
}
|
|
|
|
IRQCHIP_DECLARE(mpm_gic_chip, "qcom,mpm-gic", mpm_gic_chip_init);
|
|
|
|
static int __init mpm_gpio_chip_init(struct device_node *node,
|
|
struct device_node *parent)
|
|
{
|
|
const struct of_device_id *id;
|
|
|
|
id = of_match_node(mpm_gpio_chip_data_table, node);
|
|
if (!id) {
|
|
pr_err("match_table not found for mpm-gpio\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
msm_mpm_dev_data.gpio_chip_domain = irq_domain_create_linear(
|
|
of_node_to_fwnode(node), num_mpm_irqs,
|
|
&msm_mpm_gpio_chip_domain_ops, (void *)id->data);
|
|
|
|
if (!msm_mpm_dev_data.gpio_chip_domain)
|
|
return -ENOMEM;
|
|
|
|
return 0;
|
|
}
|
|
|
|
IRQCHIP_DECLARE(mpm_gpio_chip, "qcom,mpm-gpio", mpm_gpio_chip_init);
|
|
|