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290 lines
7.7 KiB
290 lines
7.7 KiB
/*
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* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _DP_PARSER_H_
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#define _DP_PARSER_H_
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#include <linux/sde_io_util.h>
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#define DP_LABEL "MDSS DP DISPLAY"
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#define AUX_CFG_LEN 10
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#define DP_MAX_PIXEL_CLK_KHZ 675000
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#define DP_MAX_LINK_CLK_KHZ 810000
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#define MAX_DP_MST_STREAMS 2
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enum dp_pm_type {
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DP_CORE_PM,
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DP_CTRL_PM,
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DP_PHY_PM,
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DP_STREAM0_PM,
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DP_STREAM1_PM,
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DP_LINK_PM,
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DP_MAX_PM
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};
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static inline const char *dp_parser_pm_name(enum dp_pm_type module)
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{
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switch (module) {
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case DP_CORE_PM: return "DP_CORE_PM";
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case DP_CTRL_PM: return "DP_CTRL_PM";
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case DP_PHY_PM: return "DP_PHY_PM";
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case DP_STREAM0_PM: return "DP_STREAM0_PM";
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case DP_STREAM1_PM: return "DP_STREAM1_PM";
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case DP_LINK_PM: return "DP_LINK_PM";
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default: return "???";
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}
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}
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/**
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* struct dp_display_data - display related device tree data.
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*
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* @ctrl_node: referece to controller device
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* @phy_node: reference to phy device
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* @is_active: is the controller currently active
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* @name: name of the display
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* @display_type: type of the display
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*/
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struct dp_display_data {
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struct device_node *ctrl_node;
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struct device_node *phy_node;
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bool is_active;
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const char *name;
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const char *display_type;
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};
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/**
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* struct dp_io_data - data structure to store DP IO related info
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* @name: name of the IO
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* @buf: buffer corresponding to IO for debugging
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* @io: io data which give len and mapped address
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*/
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struct dp_io_data {
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const char *name;
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u8 *buf;
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struct dss_io_data io;
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};
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/**
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* struct dp_io - data struct to store array of DP IO info
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* @len: total number of IOs
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* @data: pointer to an array of DP IO data structures.
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*/
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struct dp_io {
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u32 len;
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struct dp_io_data *data;
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};
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/**
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* struct dp_pinctrl - DP's pin control
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*
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* @pin: pin-controller's instance
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* @state_active: active state pin control
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* @state_hpd_active: hpd active state pin control
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* @state_suspend: suspend state pin control
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*/
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struct dp_pinctrl {
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struct pinctrl *pin;
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struct pinctrl_state *state_active;
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struct pinctrl_state *state_hpd_active;
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struct pinctrl_state *state_hpd_tlmm;
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struct pinctrl_state *state_hpd_ctrl;
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struct pinctrl_state *state_suspend;
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};
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#define DP_ENUM_STR(x) #x
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#define DP_AUX_CFG_MAX_VALUE_CNT 3
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/**
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* struct dp_aux_cfg - DP's AUX configuration settings
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*
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* @cfg_cnt: count of the configurable settings for the AUX register
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* @current_index: current index of the AUX config lut
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* @offset: register offset of the AUX config register
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* @lut: look up table for the AUX config values for this register
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*/
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struct dp_aux_cfg {
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u32 cfg_cnt;
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u32 current_index;
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u32 offset;
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u32 lut[DP_AUX_CFG_MAX_VALUE_CNT];
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};
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/* PHY AUX config registers */
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enum dp_phy_aux_config_type {
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PHY_AUX_CFG0,
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PHY_AUX_CFG1,
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PHY_AUX_CFG2,
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PHY_AUX_CFG3,
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PHY_AUX_CFG4,
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PHY_AUX_CFG5,
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PHY_AUX_CFG6,
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PHY_AUX_CFG7,
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PHY_AUX_CFG8,
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PHY_AUX_CFG9,
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PHY_AUX_CFG_MAX,
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};
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/**
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* enum dp_phy_version - version of the dp phy
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* @DP_PHY_VERSION_UNKNOWN: Unknown controller version
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* @DP_PHY_VERSION_4_2_0: DP phy v4.2.0 controller
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* @DP_PHY_VERSION_MAX: max version
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*/
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enum dp_phy_version {
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DP_PHY_VERSION_UNKNOWN,
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DP_PHY_VERSION_2_0_0 = 0x200,
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DP_PHY_VERSION_4_2_0 = 0x420,
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DP_PHY_VERSION_MAX
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};
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/**
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* struct dp_hw_cfg - DP HW specific configuration
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*
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* @phy_version: DP PHY HW version
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*/
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struct dp_hw_cfg {
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enum dp_phy_version phy_version;
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};
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static inline char *dp_phy_aux_config_type_to_string(u32 cfg_type)
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{
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switch (cfg_type) {
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case PHY_AUX_CFG0:
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return DP_ENUM_STR(PHY_AUX_CFG0);
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case PHY_AUX_CFG1:
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return DP_ENUM_STR(PHY_AUX_CFG1);
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case PHY_AUX_CFG2:
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return DP_ENUM_STR(PHY_AUX_CFG2);
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case PHY_AUX_CFG3:
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return DP_ENUM_STR(PHY_AUX_CFG3);
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case PHY_AUX_CFG4:
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return DP_ENUM_STR(PHY_AUX_CFG4);
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case PHY_AUX_CFG5:
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return DP_ENUM_STR(PHY_AUX_CFG5);
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case PHY_AUX_CFG6:
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return DP_ENUM_STR(PHY_AUX_CFG6);
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case PHY_AUX_CFG7:
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return DP_ENUM_STR(PHY_AUX_CFG7);
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case PHY_AUX_CFG8:
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return DP_ENUM_STR(PHY_AUX_CFG8);
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case PHY_AUX_CFG9:
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return DP_ENUM_STR(PHY_AUX_CFG9);
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default:
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return "unknown";
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}
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}
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/**
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* struct dp_parser - DP parser's data exposed to clients
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*
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* @pdev: platform data of the client
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* @msm_hdcp_dev: device pointer for the HDCP driver
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* @mp: gpio, regulator and clock related data
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* @pinctrl: pin-control related data
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* @disp_data: controller's display related data
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* @l_pnswap: P/N swap status on each lane
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* @max_pclk_khz: maximum pixel clock supported for the platform
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* @max_lclk_khz: maximum link clock supported for the platform
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* @max_hdisplay: maximum supported horizontal display by the platform for dp
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* @max_vdisplay: maximum supported vertical display by the platform for dp
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* @no_mst_encoder: zero mst encoders should be initialised for platform
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* @hw_cfg: DP HW specific settings
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* @has_mst: MST feature enable status
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* @has_mst_sideband: MST sideband feature enable status
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* @no_aux_switch: presence AUX switch status
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* @gpio_aux_switch: presence GPIO AUX switch status
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* @dsc_feature_enable: DSC feature enable status
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* @fec_feature_enable: FEC feature enable status
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* @max_dp_dsc_blks: maximum DSC blks for DP interface
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* @max_dp_dsc_input_width_pixs: Maximum input width for DSC block
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* @has_widebus: widebus (2PPC) feature eanble status
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* @mst_fixed_port: mst port_num reserved for fixed topology
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* @mst_fixed_display_type: mst display_type reserved for fixed topology
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* @display_type: display type as defined in device tree.
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* @parse: function to be called by client to parse device tree.
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* @get_io: function to be called by client to get io data.
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* @get_io_buf: function to be called by client to get io buffers.
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* @clear_io_buf: function to be called by client to clear io buffers.
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*/
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struct dp_parser {
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struct platform_device *pdev;
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struct device *msm_hdcp_dev;
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struct dss_module_power mp[DP_MAX_PM];
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struct dp_pinctrl pinctrl;
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struct dp_io io;
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struct dp_display_data disp_data;
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u8 l_map[4];
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u8 l_pnswap;
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struct dp_aux_cfg aux_cfg[AUX_CFG_LEN];
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u32 max_pclk_khz;
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u32 max_lclk_khz;
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u32 max_hdisplay;
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u32 max_vdisplay;
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bool no_mst_encoder;
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struct dp_hw_cfg hw_cfg;
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bool has_mst;
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bool has_mst_sideband;
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bool no_aux_switch;
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bool dsc_feature_enable;
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bool fec_feature_enable;
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bool has_widebus;
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bool gpio_aux_switch;
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u32 max_dp_dsc_blks;
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u32 max_dp_dsc_input_width_pixs;
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bool lphw_hpd;
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u32 mst_fixed_port[MAX_DP_MST_STREAMS];
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const char *mst_fixed_display_type[MAX_DP_MST_STREAMS];
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const char *display_type;
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int (*parse)(struct dp_parser *parser);
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struct dp_io_data *(*get_io)(struct dp_parser *parser, char *name);
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void (*get_io_buf)(struct dp_parser *parser, char *name);
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void (*clear_io_buf)(struct dp_parser *parser);
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};
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enum dp_phy_lane_num {
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DP_PHY_LN0 = 0,
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DP_PHY_LN1 = 1,
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DP_PHY_LN2 = 2,
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DP_PHY_LN3 = 3,
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DP_MAX_PHY_LN = 4,
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};
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enum dp_mainlink_lane_num {
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DP_ML0 = 0,
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DP_ML1 = 1,
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DP_ML2 = 2,
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DP_ML3 = 3,
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};
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/**
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* dp_parser_get() - get the DP's device tree parser module
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*
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* @pdev: platform data of the client
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* return: pointer to dp_parser structure.
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*
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* This function provides client capability to parse the
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* device tree and populate the data structures. The data
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* related to clock, regulators, pin-control and other
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* can be parsed using this module.
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*/
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struct dp_parser *dp_parser_get(struct platform_device *pdev);
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/**
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* dp_parser_put() - cleans the dp_parser module
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*
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* @parser: pointer to the parser's data.
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*/
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void dp_parser_put(struct dp_parser *parser);
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#endif
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