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269 lines
6.5 KiB
269 lines
6.5 KiB
/* Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MDSS_PLL_H
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#define __MDSS_PLL_H
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/regmap.h>
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#include "../clk-regmap.h"
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#include "../clk-regmap-divider.h"
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#include "../clk-regmap-mux.h"
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#if defined(CONFIG_DRM)
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#include <linux/sde_io_util.h>
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#else
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#include <linux/mdss_io_util.h>
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#endif
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#define MDSS_PLL_REG_W(base, offset, data) \
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writel_relaxed((data), (base) + (offset))
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#define MDSS_PLL_REG_R(base, offset) readl_relaxed((base) + (offset))
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#define PLL_CALC_DATA(addr0, addr1, data0, data1) \
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(((data1) << 24) | ((((addr1) / 4) & 0xFF) << 16) | \
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((data0) << 8) | (((addr0) / 4) & 0xFF))
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#define MDSS_DYN_PLL_REG_W(base, offset, addr0, addr1, data0, data1) \
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writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \
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(base) + (offset))
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#define upper_8_bit(x) ((((x) >> 2) & 0x100) >> 8)
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enum {
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MDSS_DSI_PLL_10NM,
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MDSS_DP_PLL_10NM,
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MDSS_DSI_PLL_7NM,
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MDSS_DSI_PLL_7NM_V2,
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MDSS_DP_PLL_7NM,
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MDSS_DSI_PLL_28LPM,
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MDSS_DSI_PLL_14NM,
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MDSS_DP_PLL_14NM,
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MDSS_HDMI_PLL_28LPM,
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MDSS_DSI_PLL_12NM,
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MDSS_UNKNOWN_PLL,
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};
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enum {
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MDSS_PLL_TARGET_8996,
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MDSS_PLL_TARGET_SDM660,
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};
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#define DFPS_MAX_NUM_OF_FRAME_RATES 16
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struct dfps_pll_codes {
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uint32_t pll_codes_1;
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uint32_t pll_codes_2;
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uint32_t pll_codes_3;
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};
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struct dfps_codes_info {
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uint32_t is_valid;
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uint32_t clk_rate; /* hz */
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struct dfps_pll_codes pll_codes;
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};
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struct dfps_info {
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uint32_t vco_rate_cnt;
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struct dfps_codes_info codes_dfps[DFPS_MAX_NUM_OF_FRAME_RATES];
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};
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struct mdss_pll_resources {
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/* Pll specific resources like GPIO, power supply, clocks, etc*/
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struct dss_module_power mp;
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/*
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* dsi/edp/hmdi plls' base register, phy, gdsc and dynamic refresh
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* register mapping
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*/
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void __iomem *pll_base;
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void __iomem *phy_base;
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void __iomem *ln_tx0_base;
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void __iomem *ln_tx1_base;
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void __iomem *gdsc_base;
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void __iomem *dyn_pll_base;
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bool is_init_locked;
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s64 vco_current_rate;
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s64 vco_locking_rate;
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s64 vco_ref_clk_rate;
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/*
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* Certain pll's needs to update the same vco rate after resume in
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* suspend/resume scenario. Cached the vco rate for such plls.
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*/
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unsigned long vco_cached_rate;
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u32 cached_cfg0;
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u32 cached_cfg1;
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u32 cached_outdiv;
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u32 cached_postdiv1;
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u32 cached_postdiv3;
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u32 cached_vreg_cfg;
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/* dsi/edp/hmdi pll interface type */
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u32 pll_interface_type;
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/*
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* Target ID. Used in pll_register API for valid target check before
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* registering the PLL clocks.
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*/
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u32 target_id;
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/* HW recommended delay during configuration of vco clock rate */
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u32 vco_delay;
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/* Ref-count of the PLL resources */
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u32 resource_ref_cnt;
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/*
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* Keep track to resource status to avoid updating same status for the
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* pll from different paths
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*/
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bool resource_enable;
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/*
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* Certain plls' do not allow vco rate update if it is on. Keep track of
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* status for them to turn on/off after set rate success.
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*/
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bool pll_on;
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/*
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* handoff_status is true of pll is already enabled by bootloader with
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* continuous splash enable case. Clock API will call the handoff API
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* to enable the status. It is disabled if continuous splash
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* feature is disabled.
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*/
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bool handoff_resources;
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/*
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* caching the pll trim codes in the case of dynamic refresh
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*/
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int cache_pll_trim_codes[3];
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/*
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* for maintaining the status of saving trim codes
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*/
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bool reg_upd;
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/*
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* Notifier callback for MDSS gdsc regulator events
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*/
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struct notifier_block gdsc_cb;
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/*
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* Worker function to call PLL off event
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*/
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struct work_struct pll_off;
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/*
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* PLL index if multiple index are available. Eg. in case of
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* DSI we have 2 plls.
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*/
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uint32_t index;
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bool ssc_en; /* share pll with master */
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bool ssc_center; /* default is down spread */
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u32 ssc_freq;
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u32 ssc_ppm;
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struct mdss_pll_resources *slave;
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/*
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* target pll revision information
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*/
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int revision;
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void *priv;
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/*
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* dynamic refresh pll codes stored in this structure
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*/
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struct dfps_info *dfps;
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/*
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* for cases where dfps trigger happens before first
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* suspend/resume and handoff is not finished.
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*/
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bool dfps_trigger;
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};
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struct mdss_pll_vco_calc {
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s32 div_frac_start1;
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s32 div_frac_start2;
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s32 div_frac_start3;
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s64 dec_start1;
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s64 dec_start2;
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s64 pll_plllock_cmp1;
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s64 pll_plllock_cmp2;
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s64 pll_plllock_cmp3;
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};
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static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res)
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{
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bool ret = false;
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if (!pll_res->gdsc_base) {
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WARN(1, "gdsc_base register is not defined\n");
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return true;
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}
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if ((pll_res->target_id == MDSS_PLL_TARGET_SDM660) ||
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(pll_res->pll_interface_type == MDSS_DSI_PLL_12NM))
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ret = ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) &&
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(!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ?
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false : true;
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else
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ret = readl_relaxed(pll_res->gdsc_base) & BIT(31) ?
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false : true;
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return ret;
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}
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static inline int mdss_pll_div_prepare(struct clk_hw *hw)
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{
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struct clk_hw *parent_hw = clk_hw_get_parent(hw);
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/* Restore the divider's value */
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return hw->init->ops->set_rate(hw, clk_hw_get_rate(hw),
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clk_hw_get_rate(parent_hw));
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}
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static inline int mdss_set_mux_sel(void *context, unsigned int reg,
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unsigned int val)
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{
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return 0;
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}
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static inline int mdss_get_mux_sel(void *context, unsigned int reg,
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unsigned int *val)
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{
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*val = 0;
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return 0;
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}
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int mdss_pll_resource_enable(struct mdss_pll_resources *pll_res, bool enable);
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int mdss_pll_util_resource_init(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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void mdss_pll_util_resource_deinit(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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void mdss_pll_util_resource_release(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res,
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bool enable);
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int mdss_pll_util_resource_parse(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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void mdss_pll_util_parse_dt_dfps(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res
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, char *name);
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#endif
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