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495 lines
10 KiB
495 lines
10 KiB
/*
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* arch/ppc/platforms/pmac_nvram.c
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*
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* Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Todo: - add support for the OF persistent properties
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/bootmem.h>
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#include <linux/completion.h>
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#include <linux/spinlock.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/nvram.h>
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#define DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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#define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */
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#define CORE99_SIGNATURE 0x5a
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#define CORE99_ADLER_START 0x14
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/* On Core99, nvram is either a sharp, a micron or an AMD flash */
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#define SM_FLASH_STATUS_DONE 0x80
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#define SM_FLASH_STATUS_ERR 0x38
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#define SM_FLASH_CMD_ERASE_CONFIRM 0xd0
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#define SM_FLASH_CMD_ERASE_SETUP 0x20
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#define SM_FLASH_CMD_RESET 0xff
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#define SM_FLASH_CMD_WRITE_SETUP 0x40
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#define SM_FLASH_CMD_CLEAR_STATUS 0x50
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#define SM_FLASH_CMD_READ_STATUS 0x70
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/* CHRP NVRAM header */
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struct chrp_header {
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u8 signature;
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u8 cksum;
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u16 len;
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char name[12];
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u8 data[0];
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};
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struct core99_header {
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struct chrp_header hdr;
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u32 adler;
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u32 generation;
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u32 reserved[2];
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};
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/*
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* Read and write the non-volatile RAM on PowerMacs and CHRP machines.
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*/
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static volatile unsigned char *nvram_data;
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static int core99_bank = 0;
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// XXX Turn that into a sem
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static DEFINE_SPINLOCK(nv_lock);
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extern int system_running;
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static int (*core99_write_bank)(int bank, u8* datas);
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static int (*core99_erase_bank)(int bank);
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static char *nvram_image __pmacdata;
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static ssize_t __pmac core99_nvram_read(char *buf, size_t count, loff_t *index)
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{
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int i;
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if (nvram_image == NULL)
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return -ENODEV;
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if (*index > NVRAM_SIZE)
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return 0;
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i = *index;
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if (i + count > NVRAM_SIZE)
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count = NVRAM_SIZE - i;
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memcpy(buf, &nvram_image[i], count);
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*index = i + count;
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return count;
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}
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static ssize_t __pmac core99_nvram_write(char *buf, size_t count, loff_t *index)
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{
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int i;
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if (nvram_image == NULL)
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return -ENODEV;
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if (*index > NVRAM_SIZE)
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return 0;
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i = *index;
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if (i + count > NVRAM_SIZE)
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count = NVRAM_SIZE - i;
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memcpy(&nvram_image[i], buf, count);
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*index = i + count;
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return count;
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}
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static ssize_t __pmac core99_nvram_size(void)
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{
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if (nvram_image == NULL)
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return -ENODEV;
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return NVRAM_SIZE;
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}
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static u8 __pmac chrp_checksum(struct chrp_header* hdr)
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{
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u8 *ptr;
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u16 sum = hdr->signature;
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for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
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sum += *ptr;
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while (sum > 0xFF)
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sum = (sum & 0xFF) + (sum>>8);
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return sum;
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}
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static u32 __pmac core99_calc_adler(u8 *buffer)
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{
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int cnt;
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u32 low, high;
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buffer += CORE99_ADLER_START;
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low = 1;
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high = 0;
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for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
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if ((cnt % 5000) == 0) {
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high %= 65521UL;
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high %= 65521UL;
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}
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low += buffer[cnt];
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high += low;
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}
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low %= 65521UL;
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high %= 65521UL;
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return (high << 16) | low;
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}
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static u32 __pmac core99_check(u8* datas)
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{
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struct core99_header* hdr99 = (struct core99_header*)datas;
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if (hdr99->hdr.signature != CORE99_SIGNATURE) {
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DBG("Invalid signature\n");
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return 0;
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}
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if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
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DBG("Invalid checksum\n");
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return 0;
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}
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if (hdr99->adler != core99_calc_adler(datas)) {
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DBG("Invalid adler\n");
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return 0;
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}
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return hdr99->generation;
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}
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static int __pmac sm_erase_bank(int bank)
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{
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int stat, i;
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unsigned long timeout;
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u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
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out_8(base, SM_FLASH_CMD_ERASE_SETUP);
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out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: Sharp/Miron flash erase timeout !\n");
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break;
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}
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out_8(base, SM_FLASH_CMD_READ_STATUS);
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stat = in_8(base);
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} while (!(stat & SM_FLASH_STATUS_DONE));
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out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
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out_8(base, SM_FLASH_CMD_RESET);
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for (i=0; i<NVRAM_SIZE; i++)
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if (base[i] != 0xff) {
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printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static int __pmac sm_write_bank(int bank, u8* datas)
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{
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int i, stat = 0;
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unsigned long timeout;
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u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
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for (i=0; i<NVRAM_SIZE; i++) {
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out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
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udelay(1);
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out_8(base+i, datas[i]);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
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break;
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}
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out_8(base, SM_FLASH_CMD_READ_STATUS);
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stat = in_8(base);
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} while (!(stat & SM_FLASH_STATUS_DONE));
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if (!(stat & SM_FLASH_STATUS_DONE))
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break;
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}
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out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
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out_8(base, SM_FLASH_CMD_RESET);
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for (i=0; i<NVRAM_SIZE; i++)
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if (base[i] != datas[i]) {
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printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static int __pmac amd_erase_bank(int bank)
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{
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int i, stat = 0;
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unsigned long timeout;
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u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: AMD Erasing bank %d...\n", bank);
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/* Unlock 1 */
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out_8(base+0x555, 0xaa);
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udelay(1);
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/* Unlock 2 */
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out_8(base+0x2aa, 0x55);
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udelay(1);
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/* Sector-Erase */
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out_8(base+0x555, 0x80);
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udelay(1);
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out_8(base+0x555, 0xaa);
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udelay(1);
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out_8(base+0x2aa, 0x55);
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udelay(1);
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out_8(base, 0x30);
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udelay(1);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
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break;
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}
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stat = in_8(base) ^ in_8(base);
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} while (stat != 0);
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/* Reset */
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out_8(base, 0xf0);
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udelay(1);
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for (i=0; i<NVRAM_SIZE; i++)
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if (base[i] != 0xff) {
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printk(KERN_ERR "nvram: AMD flash erase failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static int __pmac amd_write_bank(int bank, u8* datas)
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{
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int i, stat = 0;
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unsigned long timeout;
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u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
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DBG("nvram: AMD Writing bank %d...\n", bank);
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for (i=0; i<NVRAM_SIZE; i++) {
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/* Unlock 1 */
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out_8(base+0x555, 0xaa);
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udelay(1);
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/* Unlock 2 */
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out_8(base+0x2aa, 0x55);
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udelay(1);
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/* Write single word */
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out_8(base+0x555, 0xa0);
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udelay(1);
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out_8(base+i, datas[i]);
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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printk(KERN_ERR "nvram: AMD flash write timeout !\n");
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break;
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}
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stat = in_8(base) ^ in_8(base);
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} while (stat != 0);
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if (stat != 0)
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break;
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}
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/* Reset */
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out_8(base, 0xf0);
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udelay(1);
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for (i=0; i<NVRAM_SIZE; i++)
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if (base[i] != datas[i]) {
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printk(KERN_ERR "nvram: AMD flash write failed !\n");
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return -ENXIO;
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}
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return 0;
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}
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static int __pmac core99_nvram_sync(void)
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{
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struct core99_header* hdr99;
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unsigned long flags;
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spin_lock_irqsave(&nv_lock, flags);
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if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
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NVRAM_SIZE))
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goto bail;
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DBG("Updating nvram...\n");
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hdr99 = (struct core99_header*)nvram_image;
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hdr99->generation++;
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hdr99->hdr.signature = CORE99_SIGNATURE;
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hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
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hdr99->adler = core99_calc_adler(nvram_image);
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core99_bank = core99_bank ? 0 : 1;
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if (core99_erase_bank)
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if (core99_erase_bank(core99_bank)) {
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printk("nvram: Error erasing bank %d\n", core99_bank);
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goto bail;
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}
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if (core99_write_bank)
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if (core99_write_bank(core99_bank, nvram_image))
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printk("nvram: Error writing bank %d\n", core99_bank);
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bail:
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spin_unlock_irqrestore(&nv_lock, flags);
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return 0;
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}
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int __init pmac_nvram_init(void)
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{
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struct device_node *dp;
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u32 gen_bank0, gen_bank1;
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int i;
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dp = find_devices("nvram");
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if (dp == NULL) {
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printk(KERN_ERR "Can't find NVRAM device\n");
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return -ENODEV;
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}
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if (!device_is_compatible(dp, "nvram,flash")) {
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printk(KERN_ERR "Incompatible type of NVRAM\n");
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return -ENXIO;
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}
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nvram_image = alloc_bootmem(NVRAM_SIZE);
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if (nvram_image == NULL) {
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printk(KERN_ERR "nvram: can't allocate ram image\n");
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return -ENOMEM;
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}
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nvram_data = ioremap(dp->addrs[0].address, NVRAM_SIZE*2);
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DBG("nvram: Checking bank 0...\n");
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gen_bank0 = core99_check((u8 *)nvram_data);
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gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
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core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
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DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
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DBG("nvram: Active bank is: %d\n", core99_bank);
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for (i=0; i<NVRAM_SIZE; i++)
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nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
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ppc_md.nvram_read = core99_nvram_read;
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ppc_md.nvram_write = core99_nvram_write;
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ppc_md.nvram_size = core99_nvram_size;
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ppc_md.nvram_sync = core99_nvram_sync;
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/*
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* Maybe we could be smarter here though making an exclusive list
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* of known flash chips is a bit nasty as older OF didn't provide us
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* with a useful "compatible" entry. A solution would be to really
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* identify the chip using flash id commands and base ourselves on
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* a list of known chips IDs
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*/
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if (device_is_compatible(dp, "amd-0137")) {
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core99_erase_bank = amd_erase_bank;
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core99_write_bank = amd_write_bank;
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} else {
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core99_erase_bank = sm_erase_bank;
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core99_write_bank = sm_write_bank;
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}
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return 0;
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}
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int __pmac pmac_get_partition(int partition)
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{
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struct nvram_partition *part;
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const char *name;
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int sig;
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switch(partition) {
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case pmac_nvram_OF:
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name = "common";
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sig = NVRAM_SIG_SYS;
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break;
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case pmac_nvram_XPRAM:
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name = "APL,MacOS75";
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sig = NVRAM_SIG_OS;
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break;
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case pmac_nvram_NR:
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default:
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/* Oldworld stuff */
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return -ENODEV;
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}
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part = nvram_find_partition(sig, name);
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if (part == NULL)
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return 0;
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return part->index;
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}
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u8 __pmac pmac_xpram_read(int xpaddr)
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{
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int offset = pmac_get_partition(pmac_nvram_XPRAM);
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loff_t index;
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u8 buf;
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ssize_t count;
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if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
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return 0xff;
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index = offset + xpaddr;
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count = ppc_md.nvram_read(&buf, 1, &index);
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if (count != 1)
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return 0xff;
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return buf;
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}
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void __pmac pmac_xpram_write(int xpaddr, u8 data)
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{
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int offset = pmac_get_partition(pmac_nvram_XPRAM);
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loff_t index;
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u8 buf;
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if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
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return;
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index = offset + xpaddr;
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buf = data;
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ppc_md.nvram_write(&buf, 1, &index);
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}
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EXPORT_SYMBOL(pmac_get_partition);
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EXPORT_SYMBOL(pmac_xpram_read);
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EXPORT_SYMBOL(pmac_xpram_write);
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