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162 lines
7.0 KiB
162 lines
7.0 KiB
/*
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* Hardware definitions for TI OMAP1510 processor.
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*
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* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_ARCH_OMAP15XX_H
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#define __ASM_ARCH_OMAP15XX_H
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/*
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* ----------------------------------------------------------------------------
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* Base addresses
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* ----------------------------------------------------------------------------
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*/
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/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
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#define OMAP1510_DSP_BASE 0xE0000000
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#define OMAP1510_DSP_SIZE 0x28000
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#define OMAP1510_DSP_START 0xE0000000
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#define OMAP1510_DSPREG_BASE 0xE1000000
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#define OMAP1510_DSPREG_SIZE SZ_128K
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#define OMAP1510_DSPREG_START 0xE1000000
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#define OMAP1510_DSP_MMU_BASE (0xfffed200)
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/*
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* ---------------------------------------------------------------------------
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* OMAP-1510 FPGA
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* ---------------------------------------------------------------------------
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*/
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#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */
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#define OMAP1510_FPGA_SIZE SZ_4K
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#define OMAP1510_FPGA_START 0x08000000 /* PA */
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/* Revision */
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#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
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#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)
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#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2)
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#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3)
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#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4)
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#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5)
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/* Interrupt status */
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#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6)
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#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7)
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/* Interrupt mask */
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#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8)
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#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9)
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/* Reset registers */
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#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa)
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#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb)
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#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc)
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#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe)
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#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf)
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#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14)
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#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15)
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#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16)
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#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18)
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#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c)
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#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100)
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#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101)
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#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102)
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#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204)
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#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205)
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#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206)
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#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207)
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#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208)
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#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209)
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#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a)
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#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b)
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#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d)
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#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e)
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#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210)
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#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
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/*
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* Power up Giga UART driver, turn on HID clock.
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* Turn off BT power, since we're not using it and it
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* draws power.
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*/
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#define OMAP1510_FPGA_RESET_VALUE 0x42
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#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
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#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
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#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
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#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
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#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
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#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
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#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
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#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
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/*
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* Innovator/OMAP1510 FPGA HID register bit definitions
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*/
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#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
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#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
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#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
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#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
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#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
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#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
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#define OMAP1510_FPGA_HID_rsrvd (1<<6)
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#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
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/* The FPGA IRQ is cascaded through GPIO_13 */
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#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
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/* IRQ Numbers for interrupts muxed through the FPGA */
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#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
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#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
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#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
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#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
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#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
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#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
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#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
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#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
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#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
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#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
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#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
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#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
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#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
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#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
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#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
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#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
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#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
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#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
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#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
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#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
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#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
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#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
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#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
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#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
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#endif /* __ASM_ARCH_OMAP15XX_H */
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