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347 lines
8.5 KiB
347 lines
8.5 KiB
/*
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* AMD 76x Memory Controller kernel module
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* (C) 2003 Linux Networx (http://lnxi.com)
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* Written by Thayne Harbaugh
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* Based on work by Dan Hollis <goemon at anime dot net> and others.
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* http://www.anime.net/~goemon/linux-ecc/
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*
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* $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/slab.h>
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#include "edac_mc.h"
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#define AMD76X_REVISION " Ver: 2.0.1 " __DATE__
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#define EDAC_MOD_STR "amd76x_edac"
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#define amd76x_printk(level, fmt, arg...) \
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edac_printk(level, "amd76x", fmt, ##arg)
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#define amd76x_mc_printk(mci, level, fmt, arg...) \
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edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
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#define AMD76X_NR_CSROWS 8
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#define AMD76X_NR_CHANS 1
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#define AMD76X_NR_DIMMS 4
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/* AMD 76x register addresses - device 0 function 0 - PCI bridge */
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#define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b)
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*
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* 31:16 reserved
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* 15:14 SERR enabled: x1=ue 1x=ce
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* 13 reserved
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* 12 diag: disabled, enabled
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* 11:10 mode: dis, EC, ECC, ECC+scrub
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* 9:8 status: x1=ue 1x=ce
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* 7:4 UE cs row
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* 3:0 CE cs row
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*/
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#define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b)
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*
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* 31:26 clock disable 5 - 0
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* 25 SDRAM init
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* 24 reserved
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* 23 mode register service
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* 22:21 suspend to RAM
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* 20 burst refresh enable
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* 19 refresh disable
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* 18 reserved
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* 17:16 cycles-per-refresh
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* 15:8 reserved
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* 7:0 x4 mode enable 7 - 0
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*/
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#define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
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*
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* 31:23 chip-select base
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* 22:16 reserved
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* 15:7 chip-select mask
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* 6:3 reserved
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* 2:1 address mode
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* 0 chip-select enable
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*/
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struct amd76x_error_info {
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u32 ecc_mode_status;
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};
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enum amd76x_chips {
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AMD761 = 0,
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AMD762
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};
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struct amd76x_dev_info {
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const char *ctl_name;
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};
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static const struct amd76x_dev_info amd76x_devs[] = {
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[AMD761] = {
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.ctl_name = "AMD761"
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},
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[AMD762] = {
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.ctl_name = "AMD762"
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},
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};
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/**
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* amd76x_get_error_info - fetch error information
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* @mci: Memory controller
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* @info: Info to fill in
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*
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* Fetch and store the AMD76x ECC status. Clear pending status
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* on the chip so that further errors will be reported
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*/
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static void amd76x_get_error_info(struct mem_ctl_info *mci,
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struct amd76x_error_info *info)
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{
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struct pci_dev *pdev;
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pdev = to_pci_dev(mci->dev);
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pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
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&info->ecc_mode_status);
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if (info->ecc_mode_status & BIT(8))
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pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
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(u32) BIT(8), (u32) BIT(8));
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if (info->ecc_mode_status & BIT(9))
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pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
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(u32) BIT(9), (u32) BIT(9));
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}
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/**
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* amd76x_process_error_info - Error check
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* @mci: Memory controller
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* @info: Previously fetched information from chip
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* @handle_errors: 1 if we should do recovery
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*
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* Process the chip state and decide if an error has occurred.
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* A return of 1 indicates an error. Also if handle_errors is true
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* then attempt to handle and clean up after the error
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*/
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static int amd76x_process_error_info(struct mem_ctl_info *mci,
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struct amd76x_error_info *info, int handle_errors)
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{
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int error_found;
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u32 row;
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error_found = 0;
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/*
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* Check for an uncorrectable error
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*/
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if (info->ecc_mode_status & BIT(8)) {
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error_found = 1;
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if (handle_errors) {
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row = (info->ecc_mode_status >> 4) & 0xf;
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edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0,
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row, mci->ctl_name);
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}
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}
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/*
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* Check for a correctable error
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*/
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if (info->ecc_mode_status & BIT(9)) {
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error_found = 1;
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if (handle_errors) {
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row = info->ecc_mode_status & 0xf;
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edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0,
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0, row, 0, mci->ctl_name);
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}
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}
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return error_found;
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}
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/**
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* amd76x_check - Poll the controller
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* @mci: Memory controller
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*
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* Called by the poll handlers this function reads the status
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* from the controller and checks for errors.
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*/
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static void amd76x_check(struct mem_ctl_info *mci)
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{
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struct amd76x_error_info info;
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debugf3("%s()\n", __func__);
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amd76x_get_error_info(mci, &info);
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amd76x_process_error_info(mci, &info, 1);
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}
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static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
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enum edac_type edac_mode)
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{
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struct csrow_info *csrow;
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u32 mba, mba_base, mba_mask, dms;
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int index;
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for (index = 0; index < mci->nr_csrows; index++) {
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csrow = &mci->csrows[index];
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/* find the DRAM Chip Select Base address and mask */
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pci_read_config_dword(pdev,
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AMD76X_MEM_BASE_ADDR + (index * 4),
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&mba);
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if (!(mba & BIT(0)))
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continue;
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mba_base = mba & 0xff800000UL;
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mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
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pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
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csrow->first_page = mba_base >> PAGE_SHIFT;
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csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
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csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
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csrow->page_mask = mba_mask >> PAGE_SHIFT;
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csrow->grain = csrow->nr_pages << PAGE_SHIFT;
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csrow->mtype = MEM_RDDR;
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csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
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csrow->edac_mode = edac_mode;
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}
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}
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/**
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* amd76x_probe1 - Perform set up for detected device
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* @pdev; PCI device detected
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* @dev_idx: Device type index
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*
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* We have found an AMD76x and now need to set up the memory
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* controller status reporting. We configure and set up the
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* memory controller reporting and claim the device.
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*/
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static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
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{
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static const enum edac_type ems_modes[] = {
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EDAC_NONE,
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EDAC_EC,
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EDAC_SECDED,
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EDAC_SECDED
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};
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struct mem_ctl_info *mci = NULL;
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u32 ems;
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u32 ems_mode;
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struct amd76x_error_info discard;
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debugf0("%s()\n", __func__);
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pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
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ems_mode = (ems >> 10) & 0x3;
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mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS);
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if (mci == NULL) {
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return -ENOMEM;
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}
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debugf0("%s(): mci = %p\n", __func__, mci);
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mci->dev = &pdev->dev;
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mci->mtype_cap = MEM_FLAG_RDDR;
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
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mci->edac_cap = ems_mode ?
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(EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
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mci->mod_name = EDAC_MOD_STR;
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mci->mod_ver = AMD76X_REVISION;
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mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
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mci->edac_check = amd76x_check;
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mci->ctl_page_to_phys = NULL;
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amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
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amd76x_get_error_info(mci, &discard); /* clear counters */
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/* Here we assume that we will never see multiple instances of this
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* type of memory controller. The ID is therefore hardcoded to 0.
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*/
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if (edac_mc_add_mc(mci,0)) {
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debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
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goto fail;
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}
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/* get this far and it's successful */
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debugf3("%s(): success\n", __func__);
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return 0;
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fail:
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edac_mc_free(mci);
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return -ENODEV;
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}
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/* returns count (>= 0), or negative on error */
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static int __devinit amd76x_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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debugf0("%s()\n", __func__);
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/* don't need to call pci_device_enable() */
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return amd76x_probe1(pdev, ent->driver_data);
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}
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/**
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* amd76x_remove_one - driver shutdown
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* @pdev: PCI device being handed back
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*
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* Called when the driver is unloaded. Find the matching mci
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* structure for the device then delete the mci and free the
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* resources.
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*/
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static void __devexit amd76x_remove_one(struct pci_dev *pdev)
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{
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struct mem_ctl_info *mci;
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debugf0("%s()\n", __func__);
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if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
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return;
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edac_mc_free(mci);
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}
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static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
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{
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PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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AMD762
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},
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{
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PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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AMD761
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},
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{
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0,
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} /* 0 terminated list. */
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};
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MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
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static struct pci_driver amd76x_driver = {
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.name = EDAC_MOD_STR,
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.probe = amd76x_init_one,
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.remove = __devexit_p(amd76x_remove_one),
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.id_table = amd76x_pci_tbl,
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};
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static int __init amd76x_init(void)
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{
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return pci_register_driver(&amd76x_driver);
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}
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static void __exit amd76x_exit(void)
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{
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pci_unregister_driver(&amd76x_driver);
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}
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module_init(amd76x_init);
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module_exit(amd76x_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
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MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");
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