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308 lines
7.9 KiB
308 lines
7.9 KiB
/*
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* General Purpose functions for the global management of the
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* Communication Processor Module.
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*
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* Copyright (c) 2000 Michael Leslie <mleslie@lineo.com>
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* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
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*
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* In addition to the individual control of the communication
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* channels, there are a few functions that globally affect the
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* communication processor.
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*
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* Buffer descriptors must be allocated from the dual ported memory
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* space. The allocator for that is here. When the communication
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* process is reset, we reclaim the memory available. There is
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* currently no deallocator for this memory.
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* The amount of space available is platform dependent. On the
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* MBX, the EPPC software loads additional microcode into the
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* communication processor, and uses some of the DP ram for this
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* purpose. Current, the first 512 bytes and the last 256 bytes of
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* memory are used. Right now I am conservative and only use the
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* memory that can never be used for microcode. If there are
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* applications that require more DP ram, we can expand the boundaries
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* but then we have to be careful of any downloaded microcode.
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*
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*/
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/*
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* Michael Leslie <mleslie@lineo.com>
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* adapted Dan Malek's ppc8xx drivers to M68360
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*
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <asm/m68360.h>
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#include <asm/commproc.h>
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/* #include <asm/page.h> */
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/* #include <asm/pgtable.h> */
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extern void *_quicc_base;
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extern unsigned int system_clock;
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static uint dp_alloc_base; /* Starting offset in DP ram */
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static uint dp_alloc_top; /* Max offset + 1 */
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#if 0
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static void *host_buffer; /* One page of host buffer */
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static void *host_end; /* end + 1 */
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#endif
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/* struct cpm360_t *cpmp; */ /* Pointer to comm processor space */
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QUICC *pquicc;
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/* QUICC *quicc_dpram; */ /* mleslie - temporary; use extern pquicc elsewhere instead */
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/* CPM interrupt vector functions. */
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struct cpm_action {
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void (*handler)(void *);
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void *dev_id;
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};
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static struct cpm_action cpm_vecs[CPMVEC_NR];
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static void cpm_interrupt(int irq, void * dev, struct pt_regs * regs);
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static void cpm_error_interrupt(void *);
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/* prototypes: */
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void cpm_install_handler(int vec, void (*handler)(), void *dev_id);
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void m360_cpm_reset(void);
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void m360_cpm_reset()
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{
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/* pte_t *pte; */
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pquicc = (struct quicc *)(_quicc_base); /* initialized in crt0_rXm.S */
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/* Perform a CPM reset. */
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pquicc->cp_cr = (SOFTWARE_RESET | CMD_FLAG);
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/* Wait for CPM to become ready (should be 2 clocks). */
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while (pquicc->cp_cr & CMD_FLAG);
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/* On the recommendation of the 68360 manual, p. 7-60
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* - Set sdma interrupt service mask to 7
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* - Set sdma arbitration ID to 4
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*/
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pquicc->sdma_sdcr = 0x0740;
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/* Claim the DP memory for our use.
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*/
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dp_alloc_base = CPM_DATAONLY_BASE;
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dp_alloc_top = dp_alloc_base + CPM_DATAONLY_SIZE;
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/* Set the host page for allocation.
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*/
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/* host_buffer = host_page_addr; */
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/* host_end = host_page_addr + PAGE_SIZE; */
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/* pte = find_pte(&init_mm, host_page_addr); */
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/* pte_val(*pte) |= _PAGE_NO_CACHE; */
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/* flush_tlb_page(current->mm->mmap, host_buffer); */
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/* Tell everyone where the comm processor resides.
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*/
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/* cpmp = (cpm360_t *)commproc; */
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}
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/* This is called during init_IRQ. We used to do it above, but this
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* was too early since init_IRQ was not yet called.
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*/
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void
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cpm_interrupt_init(void)
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{
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/* Initialize the CPM interrupt controller.
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* NOTE THAT pquicc had better have been initialized!
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* reference: MC68360UM p. 7-377
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*/
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pquicc->intr_cicr =
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(CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
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(CPM_INTERRUPT << 13) |
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CICR_HP_MASK |
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(CPM_VECTOR_BASE << 5) |
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CICR_SPS;
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/* mask all CPM interrupts from reaching the cpu32 core: */
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pquicc->intr_cimr = 0;
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/* mles - If I understand correctly, the 360 just pops over to the CPM
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* specific vector, obviating the necessity to vector through the IRQ
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* whose priority the CPM is set to. This needs a closer look, though.
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*/
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/* Set our interrupt handler with the core CPU. */
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/* if (request_irq(CPM_INTERRUPT, cpm_interrupt, 0, "cpm", NULL) != 0) */
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/* panic("Could not allocate CPM IRQ!"); */
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/* Install our own error handler.
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*/
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/* I think we want to hold off on this one for the moment - mles */
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/* cpm_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL); */
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/* master CPM interrupt enable */
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/* pquicc->intr_cicr |= CICR_IEN; */ /* no such animal for 360 */
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}
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/* CPM interrupt controller interrupt.
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*/
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static void
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cpm_interrupt(int irq, void * dev, struct pt_regs * regs)
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{
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/* uint vec; */
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/* mles: Note that this stuff is currently being performed by
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* M68360_do_irq(int vec, struct pt_regs *fp), in ../ints.c */
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/* figure out the vector */
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/* call that vector's handler */
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/* clear the irq's bit in the service register */
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#if 0 /* old 860 stuff: */
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/* Get the vector by setting the ACK bit and then reading
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* the register.
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*/
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((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1;
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vec = ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr;
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vec >>= 11;
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if (cpm_vecs[vec].handler != 0)
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(*cpm_vecs[vec].handler)(cpm_vecs[vec].dev_id);
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else
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((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << vec);
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/* After servicing the interrupt, we have to remove the status
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* indicator.
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*/
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((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr |= (1 << vec);
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#endif
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}
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/* The CPM can generate the error interrupt when there is a race condition
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* between generating and masking interrupts. All we have to do is ACK it
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* and return. This is a no-op function so we don't need any special
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* tests in the interrupt handler.
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*/
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static void
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cpm_error_interrupt(void *dev)
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{
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}
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/* Install a CPM interrupt handler.
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*/
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void
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cpm_install_handler(int vec, void (*handler)(), void *dev_id)
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{
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request_irq(vec, handler, IRQ_FLG_LOCK, "timer", dev_id);
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/* if (cpm_vecs[vec].handler != 0) */
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/* printk(KERN_INFO "CPM interrupt %x replacing %x\n", */
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/* (uint)handler, (uint)cpm_vecs[vec].handler); */
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/* cpm_vecs[vec].handler = handler; */
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/* cpm_vecs[vec].dev_id = dev_id; */
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/* ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << vec); */
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/* pquicc->intr_cimr |= (1 << vec); */
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}
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/* Free a CPM interrupt handler.
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*/
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void
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cpm_free_handler(int vec)
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{
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cpm_vecs[vec].handler = NULL;
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cpm_vecs[vec].dev_id = NULL;
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/* ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << vec); */
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pquicc->intr_cimr &= ~(1 << vec);
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}
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/* Allocate some memory from the dual ported ram. We may want to
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* enforce alignment restrictions, but right now everyone is a good
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* citizen.
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*/
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uint
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m360_cpm_dpalloc(uint size)
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{
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uint retloc;
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if ((dp_alloc_base + size) >= dp_alloc_top)
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return(CPM_DP_NOSPACE);
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retloc = dp_alloc_base;
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dp_alloc_base += size;
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return(retloc);
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}
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#if 0 /* mleslie - for now these are simply kmalloc'd */
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/* We also own one page of host buffer space for the allocation of
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* UART "fifos" and the like.
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*/
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uint
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m360_cpm_hostalloc(uint size)
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{
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uint retloc;
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if ((host_buffer + size) >= host_end)
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return(0);
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retloc = host_buffer;
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host_buffer += size;
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return(retloc);
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}
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#endif
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/* Set a baud rate generator. This needs lots of work. There are
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* four BRGs, any of which can be wired to any channel.
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* The internal baud rate clock is the system clock divided by 16.
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* This assumes the baudrate is 16x oversampled by the uart.
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*/
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/* #define BRG_INT_CLK (((bd_t *)__res)->bi_intfreq * 1000000) */
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#define BRG_INT_CLK system_clock
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#define BRG_UART_CLK (BRG_INT_CLK/16)
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void
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m360_cpm_setbrg(uint brg, uint rate)
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{
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volatile uint *bp;
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/* This is good enough to get SMCs running.....
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*/
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/* bp = (uint *)&cpmp->cp_brgc1; */
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bp = (volatile uint *)(&pquicc->brgc[0].l);
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bp += brg;
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*bp = ((BRG_UART_CLK / rate - 1) << 1) | CPM_BRG_EN;
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}
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/*
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* Local variables:
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* c-indent-level: 4
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* c-basic-offset: 4
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* tab-width: 4
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* End:
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*/
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