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272 lines
7.1 KiB
272 lines
7.1 KiB
/*
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* IDE tuning and bus mastering support for the CS5510/CS5520
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* chipsets
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*
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* The CS5510/CS5520 are slightly unusual devices. Unlike the
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* typical IDE controllers they do bus mastering with the drive in
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* PIO mode and smarter silicon.
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*
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* The practical upshot of this is that we must always tune the
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* drive for the right PIO mode. We must also ignore all the blacklists
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* and the drive bus mastering DMA information.
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*
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* *** This driver is strictly experimental ***
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*
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* (c) Copyright Red Hat Inc 2002
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* For the avoidance of doubt the "preferred form" of this code is one which
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* is in an open non patent encumbered format. Where cryptographic key signing
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* forms part of the process of creating an executable the information
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* including keys needed to generate an equivalently functional executable
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* are deemed to be part of the source code.
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*
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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struct pio_clocks
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{
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int address;
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int assert;
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int recovery;
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};
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static struct pio_clocks cs5520_pio_clocks[]={
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{3, 6, 11},
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{2, 5, 6},
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{1, 4, 3},
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{1, 3, 2},
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{1, 2, 1}
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};
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static int cs5520_tune_chipset(ide_drive_t *drive, u8 xferspeed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *pdev = hwif->pci_dev;
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u8 speed = min((u8)XFER_PIO_4, xferspeed);
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int pio = speed;
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u8 reg;
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int controller = drive->dn > 1 ? 1 : 0;
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int error;
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switch(speed)
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{
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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pio -= XFER_PIO_0;
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break;
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default:
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pio = 0;
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printk(KERN_ERR "cs55x0: bad ide timing.\n");
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}
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printk("PIO clocking = %d\n", pio);
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/* FIXME: if DMA = 1 do we need to set the DMA bit here ? */
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/* 8bit CAT/CRT - 8bit command timing for channel */
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pci_write_config_byte(pdev, 0x62 + controller,
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(cs5520_pio_clocks[pio].recovery << 4) |
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(cs5520_pio_clocks[pio].assert));
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/* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
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/* FIXME: should these use address ? */
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/* Data read timing */
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pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
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(cs5520_pio_clocks[pio].recovery << 4) |
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(cs5520_pio_clocks[pio].assert));
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/* Write command timing */
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pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
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(cs5520_pio_clocks[pio].recovery << 4) |
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(cs5520_pio_clocks[pio].assert));
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/* Set the DMA enable/disable flag */
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reg = inb(hwif->dma_base + 0x02 + 8*controller);
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reg |= 1<<((drive->dn&1)+5);
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outb(reg, hwif->dma_base + 0x02 + 8*controller);
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error = ide_config_drive_speed(drive, speed);
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/* ATAPI is harder so leave it for now */
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if(!error && drive->media == ide_disk)
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error = hwif->ide_dma_on(drive);
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return error;
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}
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static void cs5520_tune_drive(ide_drive_t *drive, u8 pio)
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{
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pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
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cs5520_tune_chipset(drive, (XFER_PIO_0 + pio));
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}
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static int cs5520_config_drive_xfer_rate(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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/* Tune the drive for PIO modes up to PIO 4 */
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cs5520_tune_drive(drive, 4);
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/* Then tell the core to use DMA operations */
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return hwif->ide_dma_on(drive);
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}
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/*
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* We provide a callback for our nonstandard DMA location
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*/
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static void __devinit cs5520_init_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
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{
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unsigned long bmide = pci_resource_start(dev, 2); /* Not the usual 4 */
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if(hwif->mate && hwif->mate->dma_base) /* Second channel at primary + 8 */
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bmide += 8;
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ide_setup_dma(hwif, bmide, 8);
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}
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/*
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* We wrap the DMA activate to set the vdma flag. This is needed
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* so that the IDE DMA layer issues PIO not DMA commands over the
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* DMA channel
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*/
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static int cs5520_dma_on(ide_drive_t *drive)
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{
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drive->vdma = 1;
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return 0;
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}
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static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
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{
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hwif->tuneproc = &cs5520_tune_drive;
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hwif->speedproc = &cs5520_tune_chipset;
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hwif->ide_dma_check = &cs5520_config_drive_xfer_rate;
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hwif->ide_dma_on = &cs5520_dma_on;
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if(!noautodma)
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hwif->autodma = 1;
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if(!hwif->dma_base)
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{
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hwif->drives[0].autotune = 1;
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hwif->drives[1].autotune = 1;
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return;
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}
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hwif->atapi_dma = 0;
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hwif->ultra_mask = 0;
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hwif->swdma_mask = 0;
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hwif->mwdma_mask = 0;
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hwif->drives[0].autodma = hwif->autodma;
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hwif->drives[1].autodma = hwif->autodma;
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}
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#define DECLARE_CS_DEV(name_str) \
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{ \
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.name = name_str, \
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.init_setup_dma = cs5520_init_setup_dma, \
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.init_hwif = init_hwif_cs5520, \
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.channels = 2, \
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.autodma = AUTODMA, \
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.bootable = ON_BOARD, \
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.flags = IDEPCI_FLAG_ISA_PORTS, \
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}
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static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
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/* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
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/* 1 */ DECLARE_CS_DEV("Cyrix 5520")
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};
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/*
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* The 5510/5520 are a bit weird. They don't quite set up the way
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* the PCI helper layer expects so we must do much of the set up
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* work longhand.
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*/
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static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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ata_index_t index;
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ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];
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ide_setup_pci_noise(dev, d);
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/* We must not grab the entire device, it has 'ISA' space in its
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BARS too and we will freak out other bits of the kernel */
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if (pci_enable_device_bars(dev, 1<<2)) {
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printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
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return -ENODEV;
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}
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pci_set_master(dev);
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if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
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printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
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return -ENODEV;
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}
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index.all = 0xf0f0;
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/*
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* Now the chipset is configured we can let the core
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* do all the device setup for us
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*/
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ide_pci_setup_ports(dev, d, 14, &index);
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if((index.b.low & 0xf0) != 0xf0)
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probe_hwif_init(&ide_hwifs[index.b.low]);
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if((index.b.high & 0xf0) != 0xf0)
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probe_hwif_init(&ide_hwifs[index.b.high]);
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return 0;
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}
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static struct pci_device_id cs5520_pci_tbl[] = {
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{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
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static struct pci_driver driver = {
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.name = "Cyrix_IDE",
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.id_table = cs5520_pci_tbl,
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.probe = cs5520_init_one,
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};
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static int cs5520_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(cs5520_ide_init);
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
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MODULE_LICENSE("GPL");
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