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511 lines
13 KiB
511 lines
13 KiB
/*
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* Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818
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* Real Time Clocks/Timekeepers.
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*
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* Author: Mark A. Greer
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* mgreer@mvista.com
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*
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* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/bcd.h>
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#include <linux/mc146818rtc.h>
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#include <asm/machdep.h>
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#include <asm/io.h>
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#include <asm/time.h>
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#include <asm/todc.h>
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/*
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* Depending on the hardware on your board and your board design, the
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* RTC/NVRAM may be accessed either directly (like normal memory) or via
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* address/data registers. If your board uses the direct method, set
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* 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
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* 'nvram_as1' NULL. If your board uses address/data regs to access nvram,
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* set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
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* address of the upper byte (leave NULL if using mc146818), and set
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* 'nvram_data' to the address of the 8-bit data register.
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*
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* In order to break the assumption that the RTC and NVRAM are accessed by
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* the same mechanism, you need to explicitly set 'ppc_md.rtc_read_val' and
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* 'ppc_md.rtc_write_val', otherwise the values of 'ppc_md.rtc_read_val'
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* and 'ppc_md.rtc_write_val' will be used.
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*
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* Note: Even though the documentation for the various RTC chips say that it
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* take up to a second before it starts updating once the 'R' bit is
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* cleared, they always seem to update even though we bang on it many
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* times a second. This is true, except for the Dallas Semi 1746/1747
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* (possibly others). Those chips seem to have a real problem whenever
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* we set the 'R' bit before reading them, they basically stop counting.
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* --MAG
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*/
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/*
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* 'todc_info' should be initialized in your *_setup.c file to
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* point to a fully initialized 'todc_info_t' structure.
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* This structure holds all the register offsets for your particular
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* TODC/RTC chip.
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* TODC_ALLOC()/TODC_INIT() will allocate and initialize this table for you.
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*/
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#ifdef RTC_FREQ_SELECT
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#undef RTC_FREQ_SELECT
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#define RTC_FREQ_SELECT control_b /* Register A */
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#endif
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#ifdef RTC_CONTROL
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#undef RTC_CONTROL
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#define RTC_CONTROL control_a /* Register B */
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#endif
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#ifdef RTC_INTR_FLAGS
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#undef RTC_INTR_FLAGS
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#define RTC_INTR_FLAGS watchdog /* Register C */
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#endif
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#ifdef RTC_VALID
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#undef RTC_VALID
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#define RTC_VALID interrupts /* Register D */
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#endif
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/* Access routines when RTC accessed directly (like normal memory) */
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u_char
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todc_direct_read_val(int addr)
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{
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return readb((void __iomem *)(todc_info->nvram_data + addr));
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}
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void
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todc_direct_write_val(int addr, unsigned char val)
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{
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writeb(val, (void __iomem *)(todc_info->nvram_data + addr));
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return;
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}
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/* Access routines for accessing m48txx type chips via addr/data regs */
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u_char
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todc_m48txx_read_val(int addr)
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{
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outb(addr, todc_info->nvram_as0);
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outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
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return inb(todc_info->nvram_data);
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}
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void
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todc_m48txx_write_val(int addr, unsigned char val)
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{
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outb(addr, todc_info->nvram_as0);
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outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
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outb(val, todc_info->nvram_data);
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return;
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}
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/* Access routines for accessing mc146818 type chips via addr/data regs */
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u_char
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todc_mc146818_read_val(int addr)
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{
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outb_p(addr, todc_info->nvram_as0);
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return inb_p(todc_info->nvram_data);
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}
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void
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todc_mc146818_write_val(int addr, unsigned char val)
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{
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outb_p(addr, todc_info->nvram_as0);
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outb_p(val, todc_info->nvram_data);
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}
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/*
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* Routines to make RTC chips with NVRAM buried behind an addr/data pair
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* have the NVRAM and clock regs appear at the same level.
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* The NVRAM will appear to start at addr 0 and the clock regs will appear
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* to start immediately after the NVRAM (actually, start at offset
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* todc_info->nvram_size).
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*/
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static inline u_char
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todc_read_val(int addr)
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{
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u_char val;
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if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
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if (addr < todc_info->nvram_size) { /* NVRAM */
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ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
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val = ppc_md.rtc_read_val(todc_info->nvram_data_reg);
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}
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else { /* Clock Reg */
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addr -= todc_info->nvram_size;
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val = ppc_md.rtc_read_val(addr);
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}
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}
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else {
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val = ppc_md.rtc_read_val(addr);
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}
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return val;
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}
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static inline void
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todc_write_val(int addr, u_char val)
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{
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if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
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if (addr < todc_info->nvram_size) { /* NVRAM */
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ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
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ppc_md.rtc_write_val(todc_info->nvram_data_reg, val);
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}
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else { /* Clock Reg */
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addr -= todc_info->nvram_size;
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ppc_md.rtc_write_val(addr, val);
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}
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}
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else {
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ppc_md.rtc_write_val(addr, val);
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}
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}
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/*
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* TODC routines
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*
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* There is some ugly stuff in that there are assumptions for the mc146818.
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*
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* Assumptions:
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* - todc_info->control_a has the offset as mc146818 Register B reg
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* - todc_info->control_b has the offset as mc146818 Register A reg
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* - m48txx control reg's write enable or 'W' bit is same as
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* mc146818 Register B 'SET' bit (i.e., 0x80)
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*
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* These assumptions were made to make the code simpler.
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*/
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long __init
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todc_time_init(void)
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{
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u_char cntl_b;
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if (!ppc_md.rtc_read_val)
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ppc_md.rtc_read_val = ppc_md.nvram_read_val;
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if (!ppc_md.rtc_write_val)
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ppc_md.rtc_write_val = ppc_md.nvram_write_val;
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cntl_b = todc_read_val(todc_info->control_b);
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if (todc_info->rtc_type == TODC_TYPE_MC146818) {
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if ((cntl_b & 0x70) != 0x20) {
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printk(KERN_INFO "TODC %s %s\n",
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"real-time-clock was stopped.",
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"Now starting...");
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cntl_b &= ~0x70;
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cntl_b |= 0x20;
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}
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todc_write_val(todc_info->control_b, cntl_b);
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} else if (todc_info->rtc_type == TODC_TYPE_DS17285) {
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u_char mode;
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mode = todc_read_val(TODC_TYPE_DS17285_CNTL_A);
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/* Make sure countdown clear is not set */
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mode &= ~0x40;
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/* Enable oscillator, extended register set */
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mode |= 0x30;
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todc_write_val(TODC_TYPE_DS17285_CNTL_A, mode);
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} else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
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u_char month;
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todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
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todc_info->enable_write = TODC_DS1501_CNTL_B_TE;
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month = todc_read_val(todc_info->month);
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if ((month & 0x80) == 0x80) {
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printk(KERN_INFO "TODC %s %s\n",
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"real-time-clock was stopped.",
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"Now starting...");
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month &= ~0x80;
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todc_write_val(todc_info->month, month);
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}
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cntl_b &= ~TODC_DS1501_CNTL_B_TE;
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todc_write_val(todc_info->control_b, cntl_b);
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} else { /* must be a m48txx type */
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u_char cntl_a;
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todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
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todc_info->enable_write = TODC_MK48TXX_CNTL_A_W;
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cntl_a = todc_read_val(todc_info->control_a);
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/* Check & clear STOP bit in control B register */
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if (cntl_b & TODC_MK48TXX_DAY_CB) {
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printk(KERN_INFO "TODC %s %s\n",
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"real-time-clock was stopped.",
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"Now starting...");
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cntl_a |= todc_info->enable_write;
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cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */
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todc_write_val(todc_info->control_a, cntl_a);
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todc_write_val(todc_info->control_b, cntl_b);
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}
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/* Make sure READ & WRITE bits are cleared. */
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cntl_a &= ~(todc_info->enable_write |
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todc_info->enable_read);
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todc_write_val(todc_info->control_a, cntl_a);
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}
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return 0;
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}
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/*
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* There is some ugly stuff in that there are assumptions that for a mc146818,
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* the todc_info->control_a has the offset of the mc146818 Register B reg and
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* that the register'ss 'SET' bit is the same as the m48txx's write enable
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* bit in the control register of the m48txx (i.e., 0x80).
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*
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* It was done to make the code look simpler.
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*/
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ulong
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todc_get_rtc_time(void)
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{
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uint year = 0, mon = 0, day = 0, hour = 0, min = 0, sec = 0;
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uint limit, i;
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u_char save_control, uip = 0;
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spin_lock(&rtc_lock);
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save_control = todc_read_val(todc_info->control_a);
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if (todc_info->rtc_type != TODC_TYPE_MC146818) {
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limit = 1;
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switch (todc_info->rtc_type) {
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case TODC_TYPE_DS1553:
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case TODC_TYPE_DS1557:
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case TODC_TYPE_DS1743:
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case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
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case TODC_TYPE_DS1747:
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case TODC_TYPE_DS17285:
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break;
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default:
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todc_write_val(todc_info->control_a,
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(save_control | todc_info->enable_read));
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}
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}
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else {
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limit = 100000000;
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}
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for (i=0; i<limit; i++) {
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if (todc_info->rtc_type == TODC_TYPE_MC146818) {
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uip = todc_read_val(todc_info->RTC_FREQ_SELECT);
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}
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sec = todc_read_val(todc_info->seconds) & 0x7f;
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min = todc_read_val(todc_info->minutes) & 0x7f;
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hour = todc_read_val(todc_info->hours) & 0x3f;
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day = todc_read_val(todc_info->day_of_month) & 0x3f;
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mon = todc_read_val(todc_info->month) & 0x1f;
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year = todc_read_val(todc_info->year) & 0xff;
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if (todc_info->rtc_type == TODC_TYPE_MC146818) {
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uip |= todc_read_val(todc_info->RTC_FREQ_SELECT);
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if ((uip & RTC_UIP) == 0) break;
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}
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}
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if (todc_info->rtc_type != TODC_TYPE_MC146818) {
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switch (todc_info->rtc_type) {
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case TODC_TYPE_DS1553:
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case TODC_TYPE_DS1557:
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case TODC_TYPE_DS1743:
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case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
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case TODC_TYPE_DS1747:
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case TODC_TYPE_DS17285:
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break;
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default:
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save_control &= ~(todc_info->enable_read);
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todc_write_val(todc_info->control_a,
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save_control);
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}
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}
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spin_unlock(&rtc_lock);
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if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
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((save_control & RTC_DM_BINARY) == 0) ||
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RTC_ALWAYS_BCD) {
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BCD_TO_BIN(sec);
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BCD_TO_BIN(min);
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BCD_TO_BIN(hour);
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BCD_TO_BIN(day);
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BCD_TO_BIN(mon);
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BCD_TO_BIN(year);
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}
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year = year + 1900;
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if (year < 1970) {
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year += 100;
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}
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return mktime(year, mon, day, hour, min, sec);
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}
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int
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todc_set_rtc_time(unsigned long nowtime)
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{
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struct rtc_time tm;
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u_char save_control, save_freq_select = 0;
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spin_lock(&rtc_lock);
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to_tm(nowtime, &tm);
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save_control = todc_read_val(todc_info->control_a);
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/* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */
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todc_write_val(todc_info->control_a,
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(save_control | todc_info->enable_write));
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save_control &= ~(todc_info->enable_write); /* in case it was set */
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if (todc_info->rtc_type == TODC_TYPE_MC146818) {
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save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT);
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todc_write_val(todc_info->RTC_FREQ_SELECT,
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save_freq_select | RTC_DIV_RESET2);
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}
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tm.tm_year = (tm.tm_year - 1900) % 100;
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if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
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((save_control & RTC_DM_BINARY) == 0) ||
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RTC_ALWAYS_BCD) {
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BIN_TO_BCD(tm.tm_sec);
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BIN_TO_BCD(tm.tm_min);
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BIN_TO_BCD(tm.tm_hour);
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BIN_TO_BCD(tm.tm_mon);
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BIN_TO_BCD(tm.tm_mday);
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BIN_TO_BCD(tm.tm_year);
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}
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todc_write_val(todc_info->seconds, tm.tm_sec);
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todc_write_val(todc_info->minutes, tm.tm_min);
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todc_write_val(todc_info->hours, tm.tm_hour);
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todc_write_val(todc_info->month, tm.tm_mon);
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todc_write_val(todc_info->day_of_month, tm.tm_mday);
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todc_write_val(todc_info->year, tm.tm_year);
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todc_write_val(todc_info->control_a, save_control);
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if (todc_info->rtc_type == TODC_TYPE_MC146818) {
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todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select);
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}
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spin_unlock(&rtc_lock);
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return 0;
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}
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/*
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* Manipulates read bit to reliably read seconds at a high rate.
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*/
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static unsigned char __init todc_read_timereg(int addr)
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{
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unsigned char save_control = 0, val;
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switch (todc_info->rtc_type) {
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case TODC_TYPE_DS1553:
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case TODC_TYPE_DS1557:
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case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
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case TODC_TYPE_DS1747:
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case TODC_TYPE_DS17285:
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case TODC_TYPE_MC146818:
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break;
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default:
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save_control = todc_read_val(todc_info->control_a);
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todc_write_val(todc_info->control_a,
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(save_control | todc_info->enable_read));
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}
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val = todc_read_val(addr);
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switch (todc_info->rtc_type) {
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case TODC_TYPE_DS1553:
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case TODC_TYPE_DS1557:
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case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
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case TODC_TYPE_DS1747:
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case TODC_TYPE_DS17285:
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case TODC_TYPE_MC146818:
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break;
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default:
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save_control &= ~(todc_info->enable_read);
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todc_write_val(todc_info->control_a, save_control);
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}
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return val;
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}
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/*
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* This was taken from prep_setup.c
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* Use the NVRAM RTC to time a second to calibrate the decrementer.
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*/
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void __init
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todc_calibrate_decr(void)
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{
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ulong freq;
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ulong tbl, tbu;
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long i, loop_count;
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u_char sec;
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todc_time_init();
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/*
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* Actually this is bad for precision, we should have a loop in
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* which we only read the seconds counter. todc_read_val writes
|
|
* the address bytes on every call and this takes a lot of time.
|
|
* Perhaps an nvram_wait_change method returning a time
|
|
* stamp with a loop count as parameter would be the solution.
|
|
*/
|
|
/*
|
|
* Need to make sure the tbl doesn't roll over so if tbu increments
|
|
* during this test, we need to do it again.
|
|
*/
|
|
loop_count = 0;
|
|
|
|
sec = todc_read_timereg(todc_info->seconds) & 0x7f;
|
|
|
|
do {
|
|
tbu = get_tbu();
|
|
|
|
for (i = 0 ; i < 10000000 ; i++) {/* may take up to 1 second */
|
|
tbl = get_tbl();
|
|
|
|
if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
sec = todc_read_timereg(todc_info->seconds) & 0x7f;
|
|
|
|
for (i = 0 ; i < 10000000 ; i++) { /* Should take 1 second */
|
|
freq = get_tbl();
|
|
|
|
if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
freq -= tbl;
|
|
} while ((get_tbu() != tbu) && (++loop_count < 2));
|
|
|
|
printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
|
|
freq/1000000, freq%1000000);
|
|
|
|
tb_ticks_per_jiffy = freq / HZ;
|
|
tb_to_us = mulhwu_scale_factor(freq, 1000000);
|
|
|
|
return;
|
|
}
|
|
|