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710 lines
18 KiB
710 lines
18 KiB
/*
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* IBM PPC4xx DMA engine core library
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*
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* Copyright 2000-2004 MontaVista Software Inc.
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*
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* Cleaned up and converted to new DCR access
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* Matt Porter <mporter@kernel.crashing.org>
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*
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* Original code by Armin Kuster <akuster@mvista.com>
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* and Pete Popov <ppopov@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/miscdevice.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/dma.h>
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#include <asm/ppc4xx_dma.h>
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ppc_dma_ch_t dma_channels[MAX_PPC4xx_DMA_CHANNELS];
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int
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ppc4xx_get_dma_status(void)
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{
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return (mfdcr(DCRN_DMASR));
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}
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void
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ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr)
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{
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("set_src_addr: bad channel: %d\n", dmanr);
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return;
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}
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#ifdef PPC4xx_DMA_64BIT
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mtdcr(DCRN_DMASAH0 + dmanr*2, (u32)(src_addr >> 32));
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#else
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mtdcr(DCRN_DMASA0 + dmanr*2, (u32)src_addr);
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#endif
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}
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void
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ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr)
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{
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("set_dst_addr: bad channel: %d\n", dmanr);
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return;
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}
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#ifdef PPC4xx_DMA_64BIT
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mtdcr(DCRN_DMADAH0 + dmanr*2, (u32)(dst_addr >> 32));
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#else
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mtdcr(DCRN_DMADA0 + dmanr*2, (u32)dst_addr);
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#endif
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}
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void
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ppc4xx_enable_dma(unsigned int dmanr)
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{
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unsigned int control;
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ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
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unsigned int status_bits[] = { DMA_CS0 | DMA_TS0 | DMA_CH0_ERR,
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DMA_CS1 | DMA_TS1 | DMA_CH1_ERR,
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DMA_CS2 | DMA_TS2 | DMA_CH2_ERR,
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DMA_CS3 | DMA_TS3 | DMA_CH3_ERR};
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if (p_dma_ch->in_use) {
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printk("enable_dma: channel %d in use\n", dmanr);
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return;
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}
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("enable_dma: bad channel: %d\n", dmanr);
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return;
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}
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if (p_dma_ch->mode == DMA_MODE_READ) {
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/* peripheral to memory */
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ppc4xx_set_src_addr(dmanr, 0);
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ppc4xx_set_dst_addr(dmanr, p_dma_ch->addr);
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} else if (p_dma_ch->mode == DMA_MODE_WRITE) {
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/* memory to peripheral */
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ppc4xx_set_src_addr(dmanr, p_dma_ch->addr);
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ppc4xx_set_dst_addr(dmanr, 0);
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}
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/* for other xfer modes, the addresses are already set */
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control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
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control &= ~(DMA_TM_MASK | DMA_TD); /* clear all mode bits */
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if (p_dma_ch->mode == DMA_MODE_MM) {
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/* software initiated memory to memory */
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control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;
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}
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mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
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/*
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* Clear the CS, TS, RI bits for the channel from DMASR. This
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* has been observed to happen correctly only after the mode and
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* ETD/DCE bits in DMACRx are set above. Must do this before
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* enabling the channel.
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*/
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mtdcr(DCRN_DMASR, status_bits[dmanr]);
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/*
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* For device-paced transfers, Terminal Count Enable apparently
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* must be on, and this must be turned on after the mode, etc.
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* bits are cleared above (at least on Redwood-6).
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*/
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if ((p_dma_ch->mode == DMA_MODE_MM_DEVATDST) ||
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(p_dma_ch->mode == DMA_MODE_MM_DEVATSRC))
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control |= DMA_TCE_ENABLE;
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/*
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* Now enable the channel.
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*/
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control |= (p_dma_ch->mode | DMA_CE_ENABLE);
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mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
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p_dma_ch->in_use = 1;
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}
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void
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ppc4xx_disable_dma(unsigned int dmanr)
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{
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unsigned int control;
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ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
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if (!p_dma_ch->in_use) {
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printk("disable_dma: channel %d not in use\n", dmanr);
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return;
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}
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("disable_dma: bad channel: %d\n", dmanr);
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return;
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}
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control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
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control &= ~DMA_CE_ENABLE;
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mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
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p_dma_ch->in_use = 0;
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}
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/*
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* Sets the dma mode for single DMA transfers only.
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* For scatter/gather transfers, the mode is passed to the
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* alloc_dma_handle() function as one of the parameters.
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*
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* The mode is simply saved and used later. This allows
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* the driver to call set_dma_mode() and set_dma_addr() in
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* any order.
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*
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* Valid mode values are:
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*
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* DMA_MODE_READ peripheral to memory
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* DMA_MODE_WRITE memory to peripheral
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* DMA_MODE_MM memory to memory
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* DMA_MODE_MM_DEVATSRC device-paced memory to memory, device at src
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* DMA_MODE_MM_DEVATDST device-paced memory to memory, device at dst
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*/
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int
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ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode)
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{
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ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("set_dma_mode: bad channel 0x%x\n", dmanr);
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return DMA_STATUS_BAD_CHANNEL;
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}
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p_dma_ch->mode = mode;
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return DMA_STATUS_GOOD;
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}
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/*
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* Sets the DMA Count register. Note that 'count' is in bytes.
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* However, the DMA Count register counts the number of "transfers",
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* where each transfer is equal to the bus width. Thus, count
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* MUST be a multiple of the bus width.
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*/
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void
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ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count)
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{
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ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
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#ifdef DEBUG_4xxDMA
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{
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int error = 0;
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switch (p_dma_ch->pwidth) {
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case PW_8:
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break;
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case PW_16:
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if (count & 0x1)
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error = 1;
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break;
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case PW_32:
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if (count & 0x3)
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error = 1;
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break;
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case PW_64:
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if (count & 0x7)
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error = 1;
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break;
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default:
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printk("set_dma_count: invalid bus width: 0x%x\n",
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p_dma_ch->pwidth);
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return;
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}
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if (error)
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printk
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("Warning: set_dma_count count 0x%x bus width %d\n",
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count, p_dma_ch->pwidth);
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}
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#endif
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count = count >> p_dma_ch->shift;
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mtdcr(DCRN_DMACT0 + (dmanr * 0x8), count);
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}
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/*
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* Returns the number of bytes left to be transfered.
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* After a DMA transfer, this should return zero.
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* Reading this while a DMA transfer is still in progress will return
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* unpredictable results.
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*/
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int
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ppc4xx_get_dma_residue(unsigned int dmanr)
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{
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unsigned int count;
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ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("ppc4xx_get_dma_residue: bad channel 0x%x\n", dmanr);
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return DMA_STATUS_BAD_CHANNEL;
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}
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count = mfdcr(DCRN_DMACT0 + (dmanr * 0x8));
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return (count << p_dma_ch->shift);
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}
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/*
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* Sets the DMA address for a memory to peripheral or peripheral
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* to memory transfer. The address is just saved in the channel
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* structure for now and used later in enable_dma().
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*/
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void
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ppc4xx_set_dma_addr(unsigned int dmanr, phys_addr_t addr)
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{
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ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("ppc4xx_set_dma_addr: bad channel: %d\n", dmanr);
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return;
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}
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#ifdef DEBUG_4xxDMA
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{
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int error = 0;
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switch (p_dma_ch->pwidth) {
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case PW_8:
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break;
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case PW_16:
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if ((unsigned) addr & 0x1)
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error = 1;
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break;
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case PW_32:
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if ((unsigned) addr & 0x3)
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error = 1;
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break;
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case PW_64:
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if ((unsigned) addr & 0x7)
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error = 1;
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break;
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default:
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printk("ppc4xx_set_dma_addr: invalid bus width: 0x%x\n",
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p_dma_ch->pwidth);
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return;
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}
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if (error)
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printk("Warning: ppc4xx_set_dma_addr addr 0x%x bus width %d\n",
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addr, p_dma_ch->pwidth);
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}
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#endif
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/* save dma address and program it later after we know the xfer mode */
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p_dma_ch->addr = addr;
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}
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/*
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* Sets both DMA addresses for a memory to memory transfer.
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* For memory to peripheral or peripheral to memory transfers
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* the function set_dma_addr() should be used instead.
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*/
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void
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ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr,
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phys_addr_t dst_dma_addr)
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{
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("ppc4xx_set_dma_addr2: bad channel: %d\n", dmanr);
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return;
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}
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#ifdef DEBUG_4xxDMA
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{
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ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
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int error = 0;
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switch (p_dma_ch->pwidth) {
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case PW_8:
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break;
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case PW_16:
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if (((unsigned) src_dma_addr & 0x1) ||
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((unsigned) dst_dma_addr & 0x1)
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)
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error = 1;
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break;
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case PW_32:
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if (((unsigned) src_dma_addr & 0x3) ||
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((unsigned) dst_dma_addr & 0x3)
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)
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error = 1;
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break;
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case PW_64:
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if (((unsigned) src_dma_addr & 0x7) ||
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((unsigned) dst_dma_addr & 0x7)
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)
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error = 1;
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break;
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default:
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printk("ppc4xx_set_dma_addr2: invalid bus width: 0x%x\n",
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p_dma_ch->pwidth);
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return;
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}
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if (error)
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printk
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("Warning: ppc4xx_set_dma_addr2 src 0x%x dst 0x%x bus width %d\n",
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src_dma_addr, dst_dma_addr, p_dma_ch->pwidth);
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}
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#endif
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ppc4xx_set_src_addr(dmanr, src_dma_addr);
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ppc4xx_set_dst_addr(dmanr, dst_dma_addr);
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}
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/*
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* Enables the channel interrupt.
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*
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* If performing a scatter/gatter transfer, this function
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* MUST be called before calling alloc_dma_handle() and building
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* the sgl list. Otherwise, interrupts will not be enabled, if
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* they were previously disabled.
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*/
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int
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ppc4xx_enable_dma_interrupt(unsigned int dmanr)
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{
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unsigned int control;
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ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("ppc4xx_enable_dma_interrupt: bad channel: %d\n", dmanr);
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return DMA_STATUS_BAD_CHANNEL;
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}
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p_dma_ch->int_enable = 1;
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control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
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control |= DMA_CIE_ENABLE; /* Channel Interrupt Enable */
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mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
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return DMA_STATUS_GOOD;
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}
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/*
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* Disables the channel interrupt.
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*
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* If performing a scatter/gatter transfer, this function
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* MUST be called before calling alloc_dma_handle() and building
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* the sgl list. Otherwise, interrupts will not be disabled, if
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* they were previously enabled.
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*/
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int
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ppc4xx_disable_dma_interrupt(unsigned int dmanr)
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{
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unsigned int control;
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ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("ppc4xx_disable_dma_interrupt: bad channel: %d\n", dmanr);
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return DMA_STATUS_BAD_CHANNEL;
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}
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p_dma_ch->int_enable = 0;
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control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
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control &= ~DMA_CIE_ENABLE; /* Channel Interrupt Enable */
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mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
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return DMA_STATUS_GOOD;
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}
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/*
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* Configures a DMA channel, including the peripheral bus width, if a
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* peripheral is attached to the channel, the polarity of the DMAReq and
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* DMAAck signals, etc. This information should really be setup by the boot
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* code, since most likely the configuration won't change dynamically.
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* If the kernel has to call this function, it's recommended that it's
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* called from platform specific init code. The driver should not need to
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* call this function.
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*/
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int
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ppc4xx_init_dma_channel(unsigned int dmanr, ppc_dma_ch_t * p_init)
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{
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unsigned int polarity;
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uint32_t control = 0;
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ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
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DMA_MODE_READ = (unsigned long) DMA_TD; /* Peripheral to Memory */
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DMA_MODE_WRITE = 0; /* Memory to Peripheral */
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if (!p_init) {
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printk("ppc4xx_init_dma_channel: NULL p_init\n");
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return DMA_STATUS_NULL_POINTER;
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}
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("ppc4xx_init_dma_channel: bad channel %d\n", dmanr);
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return DMA_STATUS_BAD_CHANNEL;
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}
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#if DCRN_POL > 0
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polarity = mfdcr(DCRN_POL);
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#else
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polarity = 0;
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#endif
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/* Setup the control register based on the values passed to
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* us in p_init. Then, over-write the control register with this
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* new value.
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*/
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control |= SET_DMA_CONTROL;
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/* clear all polarity signals and then "or" in new signal levels */
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polarity &= ~GET_DMA_POLARITY(dmanr);
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polarity |= p_init->polarity;
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#if DCRN_POL > 0
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mtdcr(DCRN_POL, polarity);
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#endif
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mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
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/* save these values in our dma channel structure */
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memcpy(p_dma_ch, p_init, sizeof (ppc_dma_ch_t));
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/*
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* The peripheral width values written in the control register are:
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* PW_8 0
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* PW_16 1
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* PW_32 2
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* PW_64 3
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*
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* Since the DMA count register takes the number of "transfers",
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* we need to divide the count sent to us in certain
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* functions by the appropriate number. It so happens that our
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* right shift value is equal to the peripheral width value.
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*/
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p_dma_ch->shift = p_init->pwidth;
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/*
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* Save the control word for easy access.
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*/
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p_dma_ch->control = control;
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mtdcr(DCRN_DMASR, 0xffffffff); /* clear status register */
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return DMA_STATUS_GOOD;
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}
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/*
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* This function returns the channel configuration.
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*/
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int
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ppc4xx_get_channel_config(unsigned int dmanr, ppc_dma_ch_t * p_dma_ch)
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{
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unsigned int polarity;
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unsigned int control;
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if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
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printk("ppc4xx_get_channel_config: bad channel %d\n", dmanr);
|
|
return DMA_STATUS_BAD_CHANNEL;
|
|
}
|
|
|
|
memcpy(p_dma_ch, &dma_channels[dmanr], sizeof (ppc_dma_ch_t));
|
|
|
|
#if DCRN_POL > 0
|
|
polarity = mfdcr(DCRN_POL);
|
|
#else
|
|
polarity = 0;
|
|
#endif
|
|
|
|
p_dma_ch->polarity = polarity & GET_DMA_POLARITY(dmanr);
|
|
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
|
|
|
|
p_dma_ch->cp = GET_DMA_PRIORITY(control);
|
|
p_dma_ch->pwidth = GET_DMA_PW(control);
|
|
p_dma_ch->psc = GET_DMA_PSC(control);
|
|
p_dma_ch->pwc = GET_DMA_PWC(control);
|
|
p_dma_ch->phc = GET_DMA_PHC(control);
|
|
p_dma_ch->ce = GET_DMA_CE_ENABLE(control);
|
|
p_dma_ch->int_enable = GET_DMA_CIE_ENABLE(control);
|
|
p_dma_ch->shift = GET_DMA_PW(control);
|
|
|
|
#ifdef CONFIG_PPC4xx_EDMA
|
|
p_dma_ch->pf = GET_DMA_PREFETCH(control);
|
|
#else
|
|
p_dma_ch->ch_enable = GET_DMA_CH(control);
|
|
p_dma_ch->ece_enable = GET_DMA_ECE(control);
|
|
p_dma_ch->tcd_disable = GET_DMA_TCD(control);
|
|
#endif
|
|
return DMA_STATUS_GOOD;
|
|
}
|
|
|
|
/*
|
|
* Sets the priority for the DMA channel dmanr.
|
|
* Since this is setup by the hardware init function, this function
|
|
* can be used to dynamically change the priority of a channel.
|
|
*
|
|
* Acceptable priorities:
|
|
*
|
|
* PRIORITY_LOW
|
|
* PRIORITY_MID_LOW
|
|
* PRIORITY_MID_HIGH
|
|
* PRIORITY_HIGH
|
|
*
|
|
*/
|
|
int
|
|
ppc4xx_set_channel_priority(unsigned int dmanr, unsigned int priority)
|
|
{
|
|
unsigned int control;
|
|
|
|
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
|
|
printk("ppc4xx_set_channel_priority: bad channel %d\n", dmanr);
|
|
return DMA_STATUS_BAD_CHANNEL;
|
|
}
|
|
|
|
if ((priority != PRIORITY_LOW) &&
|
|
(priority != PRIORITY_MID_LOW) &&
|
|
(priority != PRIORITY_MID_HIGH) && (priority != PRIORITY_HIGH)) {
|
|
printk("ppc4xx_set_channel_priority: bad priority: 0x%x\n", priority);
|
|
}
|
|
|
|
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
|
|
control |= SET_DMA_PRIORITY(priority);
|
|
mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
|
|
|
|
return DMA_STATUS_GOOD;
|
|
}
|
|
|
|
/*
|
|
* Returns the width of the peripheral attached to this channel. This assumes
|
|
* that someone who knows the hardware configuration, boot code or some other
|
|
* init code, already set the width.
|
|
*
|
|
* The return value is one of:
|
|
* PW_8
|
|
* PW_16
|
|
* PW_32
|
|
* PW_64
|
|
*
|
|
* The function returns 0 on error.
|
|
*/
|
|
unsigned int
|
|
ppc4xx_get_peripheral_width(unsigned int dmanr)
|
|
{
|
|
unsigned int control;
|
|
|
|
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
|
|
printk("ppc4xx_get_peripheral_width: bad channel %d\n", dmanr);
|
|
return DMA_STATUS_BAD_CHANNEL;
|
|
}
|
|
|
|
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
|
|
|
|
return (GET_DMA_PW(control));
|
|
}
|
|
|
|
/*
|
|
* Clears the channel status bits
|
|
*/
|
|
int
|
|
ppc4xx_clr_dma_status(unsigned int dmanr)
|
|
{
|
|
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
|
|
printk(KERN_ERR "ppc4xx_clr_dma_status: bad channel: %d\n", dmanr);
|
|
return DMA_STATUS_BAD_CHANNEL;
|
|
}
|
|
mtdcr(DCRN_DMASR, ((u32)DMA_CH0_ERR | (u32)DMA_CS0 | (u32)DMA_TS0) >> dmanr);
|
|
return DMA_STATUS_GOOD;
|
|
}
|
|
|
|
#ifdef CONFIG_PPC4xx_EDMA
|
|
/*
|
|
* Enables the burst on the channel (BTEN bit in the control/count register)
|
|
* Note:
|
|
* For scatter/gather dma, this function MUST be called before the
|
|
* ppc4xx_alloc_dma_handle() func as the chan count register is copied into the
|
|
* sgl list and used as each sgl element is added.
|
|
*/
|
|
int
|
|
ppc4xx_enable_burst(unsigned int dmanr)
|
|
{
|
|
unsigned int ctc;
|
|
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
|
|
printk(KERN_ERR "ppc4xx_enable_burst: bad channel: %d\n", dmanr);
|
|
return DMA_STATUS_BAD_CHANNEL;
|
|
}
|
|
ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) | DMA_CTC_BTEN;
|
|
mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
|
|
return DMA_STATUS_GOOD;
|
|
}
|
|
/*
|
|
* Disables the burst on the channel (BTEN bit in the control/count register)
|
|
* Note:
|
|
* For scatter/gather dma, this function MUST be called before the
|
|
* ppc4xx_alloc_dma_handle() func as the chan count register is copied into the
|
|
* sgl list and used as each sgl element is added.
|
|
*/
|
|
int
|
|
ppc4xx_disable_burst(unsigned int dmanr)
|
|
{
|
|
unsigned int ctc;
|
|
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
|
|
printk(KERN_ERR "ppc4xx_disable_burst: bad channel: %d\n", dmanr);
|
|
return DMA_STATUS_BAD_CHANNEL;
|
|
}
|
|
ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BTEN;
|
|
mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
|
|
return DMA_STATUS_GOOD;
|
|
}
|
|
/*
|
|
* Sets the burst size (number of peripheral widths) for the channel
|
|
* (BSIZ bits in the control/count register))
|
|
* must be one of:
|
|
* DMA_CTC_BSIZ_2
|
|
* DMA_CTC_BSIZ_4
|
|
* DMA_CTC_BSIZ_8
|
|
* DMA_CTC_BSIZ_16
|
|
* Note:
|
|
* For scatter/gather dma, this function MUST be called before the
|
|
* ppc4xx_alloc_dma_handle() func as the chan count register is copied into the
|
|
* sgl list and used as each sgl element is added.
|
|
*/
|
|
int
|
|
ppc4xx_set_burst_size(unsigned int dmanr, unsigned int bsize)
|
|
{
|
|
unsigned int ctc;
|
|
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
|
|
printk(KERN_ERR "ppc4xx_set_burst_size: bad channel: %d\n", dmanr);
|
|
return DMA_STATUS_BAD_CHANNEL;
|
|
}
|
|
ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BSIZ_MSK;
|
|
ctc |= (bsize & DMA_CTC_BSIZ_MSK);
|
|
mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
|
|
return DMA_STATUS_GOOD;
|
|
}
|
|
|
|
EXPORT_SYMBOL(ppc4xx_enable_burst);
|
|
EXPORT_SYMBOL(ppc4xx_disable_burst);
|
|
EXPORT_SYMBOL(ppc4xx_set_burst_size);
|
|
#endif /* CONFIG_PPC4xx_EDMA */
|
|
|
|
EXPORT_SYMBOL(ppc4xx_init_dma_channel);
|
|
EXPORT_SYMBOL(ppc4xx_get_channel_config);
|
|
EXPORT_SYMBOL(ppc4xx_set_channel_priority);
|
|
EXPORT_SYMBOL(ppc4xx_get_peripheral_width);
|
|
EXPORT_SYMBOL(dma_channels);
|
|
EXPORT_SYMBOL(ppc4xx_set_src_addr);
|
|
EXPORT_SYMBOL(ppc4xx_set_dst_addr);
|
|
EXPORT_SYMBOL(ppc4xx_set_dma_addr);
|
|
EXPORT_SYMBOL(ppc4xx_set_dma_addr2);
|
|
EXPORT_SYMBOL(ppc4xx_enable_dma);
|
|
EXPORT_SYMBOL(ppc4xx_disable_dma);
|
|
EXPORT_SYMBOL(ppc4xx_set_dma_mode);
|
|
EXPORT_SYMBOL(ppc4xx_set_dma_count);
|
|
EXPORT_SYMBOL(ppc4xx_get_dma_residue);
|
|
EXPORT_SYMBOL(ppc4xx_enable_dma_interrupt);
|
|
EXPORT_SYMBOL(ppc4xx_disable_dma_interrupt);
|
|
EXPORT_SYMBOL(ppc4xx_get_dma_status);
|
|
EXPORT_SYMBOL(ppc4xx_clr_dma_status);
|
|
|
|
|