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265 lines
10 KiB
265 lines
10 KiB
/*
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* Copyright (c) 2014-2018, 2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDSS_MDP_PP_DEBUG_H
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#define MDSS_MDP_PP_DEBUG_H
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#include <linux/msm_mdp.h>
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#define MDSS_BLOCK_DISP_NUM (MDP_BLOCK_MAX - MDP_LOGICAL_BLOCK_DISP_0)
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/* PP STS related flags */
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#define PP_STS_ENABLE 0x1
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#define PP_STS_GAMUT_FIRST 0x2
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#define PP_STS_PA_LUT_FIRST 0x4
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#define PP_STS_PA_HUE_MASK 0x2
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#define PP_STS_PA_SAT_MASK 0x4
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#define PP_STS_PA_VAL_MASK 0x8
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#define PP_STS_PA_CONT_MASK 0x10
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#define PP_STS_PA_MEM_PROTECT_EN 0x20
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#define PP_STS_PA_MEM_COL_SKIN_MASK 0x40
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#define PP_STS_PA_MEM_COL_FOL_MASK 0x80
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#define PP_STS_PA_MEM_COL_SKY_MASK 0x100
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#define PP_STS_PA_SIX_ZONE_HUE_MASK 0x200
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#define PP_STS_PA_SIX_ZONE_SAT_MASK 0x400
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#define PP_STS_PA_SIX_ZONE_VAL_MASK 0x800
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#define PP_STS_PA_SAT_ZERO_EXP_EN 0x1000
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#define PP_STS_PA_MEM_PROT_HUE_EN 0x2000
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#define PP_STS_PA_MEM_PROT_SAT_EN 0x4000
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#define PP_STS_PA_MEM_PROT_VAL_EN 0x8000
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#define PP_STS_PA_MEM_PROT_CONT_EN 0x10000
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#define PP_STS_PA_MEM_PROT_BLEND_EN 0x20000
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#define PP_STS_PA_MEM_PROT_SIX_EN 0x40000
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/* Demo mode macros */
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#define MDSS_SIDE_NONE 0
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#define MDSS_SIDE_LEFT 1
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#define MDSS_SIDE_RIGHT 2
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/* size calculated for c0,c1_c2 for 4 tables */
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#define GAMUT_COLOR_COEFF_SIZE_V1_7 (2 * MDP_GAMUT_TABLE_V1_7_SZ * 4)
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/* 16 entries for c0,c1,c2 */
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#define GAMUT_SCALE_OFFSET_SIZE_V1_7 (3 * MDP_GAMUT_SCALE_OFF_SZ)
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#define GAMUT_TOTAL_TABLE_SIZE_V1_7 (GAMUT_COLOR_COEFF_SIZE_V1_7 + \
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GAMUT_SCALE_OFFSET_SIZE_V1_7)
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#define GAMUT_T0_SIZE 125
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#define GAMUT_T1_SIZE 100
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#define GAMUT_T2_SIZE 80
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#define GAMUT_T3_SIZE 100
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#define GAMUT_T4_SIZE 100
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#define GAMUT_T5_SIZE 80
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#define GAMUT_T6_SIZE 64
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#define GAMUT_T7_SIZE 80
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#define GAMUT_TOTAL_TABLE_SIZE (GAMUT_T0_SIZE + GAMUT_T1_SIZE + \
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GAMUT_T2_SIZE + GAMUT_T3_SIZE + GAMUT_T4_SIZE + \
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GAMUT_T5_SIZE + GAMUT_T6_SIZE + GAMUT_T7_SIZE)
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/* Total 5 QSEED3 filters: Direction filter + Y plane cir and sep + UV plane
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* cir and sep filters
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*/
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#define QSEED3_FILTERS 5
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#define QSEED3_LUT_REGIONS 4
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enum pp_block_opmodes {
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PP_OPMODE_VIG = 1,
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PP_OPMODE_DSPP,
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PP_OPMODE_MAX
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};
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enum pp_config_block {
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SSPP_RGB = 1,
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SSPP_DMA,
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SSPP_VIG,
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DSPP,
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LM,
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PPB,
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};
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struct mdp_pp_feature_ops {
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u32 feature;
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int (*pp_get_config)(char __iomem *base_addr, void *cfg_data,
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u32 block_type, u32 disp_num);
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int (*pp_set_config)(char __iomem *base_addr,
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struct pp_sts_type *pp_sts, void *cfg_data,
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u32 block_type);
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int (*pp_get_version)(u32 *version);
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};
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struct mdp_pp_driver_ops {
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struct mdp_pp_feature_ops pp_ops[PP_MAX_FEATURES];
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void (*pp_opmode_config)(int location, struct pp_sts_type *pp_sts,
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u32 *opmode, int side);
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int (*get_hist_offset)(u32 block, u32 *ctl_off);
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int (*get_hist_isr_info)(u32 *isr_mask);
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bool (*is_sspp_hist_supp)(void);
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void (*gamut_clk_gate_en)(char __iomem *base_addr);
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int (*igc_set_dither_strength)(char __iomem *base_addr,
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struct pp_sts_type *pp_sts, void *cfg_data,
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u32 block_type);
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};
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struct mdp_pa_dither_res_data_v1_7 {
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uint32_t matrix_sz;
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uint32_t matrix_data[MDP_DITHER_DATA_V1_7_SZ];
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uint32_t strength;
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uint32_t offset_en;
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};
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struct mdss_pp_res_type_v1_7 {
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u32 pgc_lm_table_c0[MDSS_BLOCK_DISP_NUM][PGC_LUT_ENTRIES];
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u32 pgc_lm_table_c1[MDSS_BLOCK_DISP_NUM][PGC_LUT_ENTRIES];
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u32 pgc_lm_table_c2[MDSS_BLOCK_DISP_NUM][PGC_LUT_ENTRIES];
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u32 pgc_table_c0[MDSS_BLOCK_DISP_NUM][PGC_LUT_ENTRIES];
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u32 pgc_table_c1[MDSS_BLOCK_DISP_NUM][PGC_LUT_ENTRIES];
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u32 pgc_table_c2[MDSS_BLOCK_DISP_NUM][PGC_LUT_ENTRIES];
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u32 igc_table_c0_c1[MDSS_BLOCK_DISP_NUM][IGC_LUT_ENTRIES];
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u32 igc_table_c2[MDSS_BLOCK_DISP_NUM][IGC_LUT_ENTRIES];
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u32 hist_lut[MDSS_BLOCK_DISP_NUM][ENHIST_LUT_ENTRIES];
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u32 six_zone_lut_p0[MDSS_BLOCK_DISP_NUM][MDP_SIX_ZONE_LUT_SIZE];
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u32 six_zone_lut_p1[MDSS_BLOCK_DISP_NUM][MDP_SIX_ZONE_LUT_SIZE];
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struct mdp_pgc_lut_data_v1_7 pgc_dspp_v17_data[MDSS_BLOCK_DISP_NUM];
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struct mdp_pgc_lut_data_v1_7 pgc_lm_v17_data[MDSS_BLOCK_DISP_NUM];
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struct mdp_igc_lut_data_v1_7 igc_v17_data[MDSS_BLOCK_DISP_NUM];
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struct mdp_hist_lut_data_v1_7 hist_lut_v17_data[MDSS_BLOCK_DISP_NUM];
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struct mdp_dither_data_v1_7 dither_v17_data[MDSS_BLOCK_DISP_NUM];
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struct mdp_gamut_data_v1_7 gamut_v17_data[MDSS_BLOCK_DISP_NUM];
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struct mdp_pcc_data_v1_7 pcc_v17_data[MDSS_BLOCK_DISP_NUM];
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struct mdp_pa_data_v1_7 pa_v17_data[MDSS_BLOCK_DISP_NUM];
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struct mdp_pa_dither_res_data_v1_7 pa_dither_data[MDSS_BLOCK_DISP_NUM];
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};
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struct mdp_igc_lut_data_config {
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uint32_t table_fmt;
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uint32_t len;
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uint32_t *c0_c1_data;
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uint32_t *c2_data;
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uint32_t strength;
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};
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struct mdss_pp_res_type_v3 {
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int (*igc_set_config)(char __iomem *base_addr,
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struct pp_sts_type *pp_sts, void *cfg_data,
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u32 block_type);
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u32 igc_table_c0_c1[MDSS_BLOCK_DISP_NUM][IGC_LUT_ENTRIES];
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u32 igc_table_c2[MDSS_BLOCK_DISP_NUM][IGC_LUT_ENTRIES];
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struct mdp_igc_lut_data_config igc_v3_data[MDSS_BLOCK_DISP_NUM];
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};
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struct mdss_pp_res_type {
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/* logical info */
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u32 pp_disp_flags[MDSS_BLOCK_DISP_NUM];
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u32 igc_lut_c0c1[MDSS_BLOCK_DISP_NUM][IGC_LUT_ENTRIES];
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u32 igc_lut_c2[MDSS_BLOCK_DISP_NUM][IGC_LUT_ENTRIES];
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struct mdp_ar_gc_lut_data
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gc_lut_r[MDSS_BLOCK_DISP_NUM][GC_LUT_SEGMENTS];
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struct mdp_ar_gc_lut_data
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gc_lut_g[MDSS_BLOCK_DISP_NUM][GC_LUT_SEGMENTS];
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struct mdp_ar_gc_lut_data
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gc_lut_b[MDSS_BLOCK_DISP_NUM][GC_LUT_SEGMENTS];
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u32 enhist_lut[MDSS_BLOCK_DISP_NUM][ENHIST_LUT_ENTRIES];
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struct mdp_pa_cfg pa_disp_cfg[MDSS_BLOCK_DISP_NUM];
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struct mdp_pa_v2_cfg_data pa_v2_disp_cfg[MDSS_BLOCK_DISP_NUM];
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u32 six_zone_lut_curve_p0[MDSS_BLOCK_DISP_NUM][MDP_SIX_ZONE_LUT_SIZE];
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u32 six_zone_lut_curve_p1[MDSS_BLOCK_DISP_NUM][MDP_SIX_ZONE_LUT_SIZE];
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struct mdp_pcc_cfg_data pcc_disp_cfg[MDSS_BLOCK_DISP_NUM];
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struct mdp_igc_lut_data igc_disp_cfg[MDSS_BLOCK_DISP_NUM];
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struct mdp_pgc_lut_data argc_disp_cfg[MDSS_BLOCK_DISP_NUM];
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struct mdp_pgc_lut_data pgc_disp_cfg[MDSS_BLOCK_DISP_NUM];
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struct mdp_hist_lut_data enhist_disp_cfg[MDSS_BLOCK_DISP_NUM];
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struct mdp_dither_cfg_data dither_disp_cfg[MDSS_BLOCK_DISP_NUM];
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struct mdp_gamut_cfg_data gamut_disp_cfg[MDSS_BLOCK_DISP_NUM];
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uint16_t gamut_tbl[MDSS_BLOCK_DISP_NUM][GAMUT_TOTAL_TABLE_SIZE * 3];
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u32 hist_data[MDSS_BLOCK_DISP_NUM][HIST_V_SIZE];
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struct pp_sts_type pp_disp_sts[MDSS_BLOCK_DISP_NUM];
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struct mdp_dither_cfg_data pa_dither_cfg[MDSS_BLOCK_DISP_NUM];
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/* physical info */
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struct pp_hist_col_info *dspp_hist;
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/*
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* The pp_data_v1_7 will be a pointer to newer MDP revisions of the
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* pp_res, which will hold the cfg_payloads of each feature in a single
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* struct.
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*/
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void *pp_data_v1_7;
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void *pp_data_v3;
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};
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void *pp_get_driver_ops_v1_7(struct mdp_pp_driver_ops *ops);
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void *pp_get_driver_ops_v3(struct mdp_pp_driver_ops *ops);
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void *pp_get_driver_ops_stub(struct mdp_pp_driver_ops *ops);
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static inline void pp_sts_set_split_bits(u32 *sts, u32 bits)
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{
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u32 tmp = *sts;
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tmp &= ~MDSS_PP_SPLIT_MASK;
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tmp |= bits & MDSS_PP_SPLIT_MASK;
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*sts = tmp;
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}
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static inline bool pp_sts_is_enabled(u32 sts, int side)
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{
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bool ret = false;
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/*
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* If there are no sides, or if there are no split mode bits set, the
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* side can't be disabled via split mode.
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*
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* Otherwise, if the side being checked opposes the split mode
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* configuration, the side is disabled.
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*/
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if ((side == MDSS_SIDE_NONE) || !(sts & MDSS_PP_SPLIT_MASK))
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ret = true;
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else if ((sts & MDSS_PP_SPLIT_RIGHT_ONLY) && (side == MDSS_SIDE_RIGHT))
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ret = true;
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else if ((sts & MDSS_PP_SPLIT_LEFT_ONLY) && (side == MDSS_SIDE_LEFT))
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ret = true;
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return ret && (sts & PP_STS_ENABLE);
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}
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/* Debug related functions */
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void pp_print_lut(void *data, int size, char *tab, uint32_t type);
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void pp_print_uint16_lut(uint16_t *data, int size, char *tab);
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void pp_print_pcc_coeff(struct mdp_pcc_coeff *pcc_coeff, int tab_depth);
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void pp_print_pcc_cfg_data(struct mdp_pcc_cfg_data *pcc_data, int tab_depth);
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void pp_print_csc_cfg(struct mdp_csc_cfg *data, int tab_depth);
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void pp_print_csc_cfg_data(struct mdp_csc_cfg_data *data, int tab_depth);
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void pp_print_igc_lut_data(struct mdp_igc_lut_data *data, int tab_depth);
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void pp_print_ar_gc_lut_data(struct mdp_ar_gc_lut_data *data, int tab_depth);
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void pp_print_pgc_lut_data(struct mdp_pgc_lut_data *data, int tab_depth);
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void pp_print_hist_lut_data(struct mdp_hist_lut_data *data, int tab_depth);
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void pp_print_lut_cfg_data(struct mdp_lut_cfg_data *data, int tab_depth);
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void pp_print_qseed_cfg(struct mdp_qseed_cfg *data, int tab_depth);
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void pp_print_qseed_cfg_data(struct mdp_qseed_cfg_data *data, int tab_depth);
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void pp_print_pa_cfg(struct mdp_pa_cfg *data, int tab_depth);
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void pp_print_pa_cfg_data(struct mdp_pa_cfg_data *data, int tab_depth);
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void pp_print_mem_col_cfg(struct mdp_pa_mem_col_cfg *data, int tab_depth);
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void pp_print_pa_v2_data(struct mdp_pa_v2_data *data, int tab_depth);
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void pp_print_pa_v2_cfg_data(struct mdp_pa_v2_cfg_data *data, int tab_depth);
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void pp_print_dither_cfg_data(struct mdp_dither_cfg_data *data, int tab_depth);
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void pp_print_gamut_cfg_data(struct mdp_gamut_cfg_data *data, int tab_depth);
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void pp_print_ad_init(struct mdss_ad_init *data, int tab_depth);
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void pp_print_ad_cfg(struct mdss_ad_cfg *data, int tab_depth);
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void pp_print_ad_init_cfg(struct mdss_ad_init_cfg *data, int tab_depth);
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void pp_print_ad_input(struct mdss_ad_input *data, int tab_depth);
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void pp_print_histogram_cfg(struct mdp_histogram_cfg *data, int tab_depth);
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void pp_print_sharp_cfg(struct mdp_sharp_cfg *data, int tab_depth);
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void pp_print_calib_config_data(struct mdp_calib_config_data *data,
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int tab_depth);
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void pp_print_calib_config_buffer(struct mdp_calib_config_buffer *data,
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int tab_depth);
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void pp_print_calib_dcm_state(struct mdp_calib_dcm_state *data, int tab_depth);
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void pp_print_mdss_calib_cfg(struct mdss_calib_cfg *data, int tab_depth);
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#endif
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