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108 lines
3.3 KiB
108 lines
3.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Mix this utility code with some glue code to get one of several types of
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* simple SPI master driver. Two do polled word-at-a-time I/O:
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*
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* - GPIO/parport bitbangers. Provide chipselect() and txrx_word[](),
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* expanding the per-word routines from the inline templates below.
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*
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* - Drivers for controllers resembling bare shift registers. Provide
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* chipselect() and txrx_word[](), with custom setup()/cleanup() methods
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* that use your controller's clock and chipselect registers.
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*
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* Some hardware works well with requests at spi_transfer scope:
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*
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* - Drivers leveraging smarter hardware, with fifos or DMA; or for half
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* duplex (MicroWire) controllers. Provide chipselect() and txrx_bufs(),
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* and custom setup()/cleanup() methods.
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*/
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/*
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* The code that knows what GPIO pins do what should have declared four
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* functions, ideally as inlines, before including this header:
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*
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* void setsck(struct spi_device *, int is_on);
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* void setmosi(struct spi_device *, int is_on);
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* int getmiso(struct spi_device *);
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* void spidelay(unsigned);
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*
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* setsck()'s is_on parameter is a zero/nonzero boolean.
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*
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* setmosi()'s is_on parameter is a zero/nonzero boolean.
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*
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* getmiso() is required to return 0 or 1 only. Any other value is invalid
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* and will result in improper operation.
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*
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* A non-inlined routine would call bitbang_txrx_*() routines. The
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* main loop could easily compile down to a handful of instructions,
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* especially if the delay is a NOP (to run at peak speed).
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*
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* Since this is software, the timings may not be exactly what your board's
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* chips need ... there may be several reasons you'd need to tweak timings
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* in these routines, not just to make it faster or slower to match a
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* particular CPU clock rate.
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*/
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static inline u32
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bitbang_txrx_be_cpha0(struct spi_device *spi,
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unsigned nsecs, unsigned cpol, unsigned flags,
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u32 word, u8 bits)
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{
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/* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */
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u32 oldbit = (!(word & (1<<(bits-1)))) << 31;
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/* clock starts at inactive polarity */
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for (word <<= (32 - bits); likely(bits); bits--) {
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/* setup MSB (to slave) on trailing edge */
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if ((flags & SPI_MASTER_NO_TX) == 0) {
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if ((word & (1 << 31)) != oldbit) {
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setmosi(spi, word & (1 << 31));
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oldbit = word & (1 << 31);
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}
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}
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spidelay(nsecs); /* T(setup) */
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setsck(spi, !cpol);
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spidelay(nsecs);
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/* sample MSB (from slave) on leading edge */
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word <<= 1;
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if ((flags & SPI_MASTER_NO_RX) == 0)
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word |= getmiso(spi);
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setsck(spi, cpol);
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}
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return word;
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}
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static inline u32
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bitbang_txrx_be_cpha1(struct spi_device *spi,
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unsigned nsecs, unsigned cpol, unsigned flags,
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u32 word, u8 bits)
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{
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/* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */
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u32 oldbit = (!(word & (1<<(bits-1)))) << 31;
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/* clock starts at inactive polarity */
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for (word <<= (32 - bits); likely(bits); bits--) {
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/* setup MSB (to slave) on leading edge */
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setsck(spi, !cpol);
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if ((flags & SPI_MASTER_NO_TX) == 0) {
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if ((word & (1 << 31)) != oldbit) {
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setmosi(spi, word & (1 << 31));
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oldbit = word & (1 << 31);
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}
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}
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spidelay(nsecs); /* T(setup) */
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setsck(spi, cpol);
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spidelay(nsecs);
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/* sample MSB (from slave) on trailing edge */
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word <<= 1;
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if ((flags & SPI_MASTER_NO_RX) == 0)
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word |= getmiso(spi);
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}
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return word;
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}
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