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84 lines
2.7 KiB
84 lines
2.7 KiB
/* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __NQ_NCI_H
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#define __NQ_NCI_H
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#include <linux/i2c.h>
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#include <linux/types.h>
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#include <linux/version.h>
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#include <linux/semaphore.h>
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#include <linux/completion.h>
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#include <linux/ioctl.h>
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#include <linux/cdev.h>
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#include <linux/nfcinfo.h>
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#define NFC_SET_PWR _IOW(0xE9, 0x01, unsigned int)
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#define ESE_SET_PWR _IOW(0xE9, 0x02, unsigned int)
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#define ESE_GET_PWR _IOR(0xE9, 0x03, unsigned int)
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#define SET_RX_BLOCK _IOW(0xE9, 0x04, unsigned int)
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#define SET_EMULATOR_TEST_POINT _IOW(0xE9, 0x05, unsigned int)
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#define NFCC_INITIAL_CORE_RESET_NTF _IOW(0xE9, 0x10, unsigned int)
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#define NFC_RX_BUFFER_CNT_START (0x0)
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#define PAYLOAD_HEADER_LENGTH (0x3)
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#define PAYLOAD_LENGTH_MAX (256)
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#define BYTE (0x8)
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#define NCI_IDENTIFIER (0x10)
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#define DEV_COUNT 1
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#define DEVICE_NAME "nq-nci"
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#define CLASS_NAME "nqx"
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/*
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* From MW 11.04 buffer size increased to support
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* frame size of 554 in FW download mode
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* Frame len(2) + Frame Header(6) + DATA(512) + HASH(32) + CRC(2) + RFU(4)
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*/
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#define MAX_BUFFER_SIZE (558)
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#define WAKEUP_SRC_TIMEOUT (2000)
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#define MAX_RETRY_COUNT 3
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#define NCI_RESET_CMD_LEN 4
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#define NCI_RESET_RSP_LEN 6
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#define NCI_RESET_NTF_LEN 13
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#define NCI_INIT_CMD_LEN 3
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#define NCI_INIT_RSP_LEN 28
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#define NCI_GET_VERSION_CMD_LEN 8
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#define NCI_GET_VERSION_RSP_LEN 12
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#define NCI_HEADER_LEN 3
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#define NCI_1_0_RESET_RSP_PAYLOAD_LEN 3
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#define NCI_PAYLOAD_START_INDEX 3
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#define NCI_PAYLOAD_LENGTH_INDEX (NCI_PAYLOAD_START_INDEX - 1)
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#define MAX_IRQ_WAIT_TIME (90) /* in ms */
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#define NFCC_HW_CHIP_ID_OFFSET 4
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#define NFCC_HW_ROM_VER_OFFSET 3
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#define NFCC_HW_MAJOR_NO_OFFSET 2
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#define NFCC_HW_MINOR_NO_OFFSET 1
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enum nfcc_initial_core_reset_ntf {
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TIMEDOUT_INITIAL_CORE_RESET_NTF = 0, /* 0*/
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ARRIVED_INITIAL_CORE_RESET_NTF, /* 1 */
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DEFAULT_INITIAL_CORE_RESET_NTF, /*2*/
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};
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enum nfcc_chip_variant {
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NFCC_NQ_210 = 0x48, /**< NFCC NQ210 */
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NFCC_NQ_220 = 0x58, /**< NFCC NQ220 */
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NFCC_NQ_310 = 0x40, /**< NFCC NQ310 */
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NFCC_NQ_330 = 0x51, /**< NFCC NQ330 */
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NFCC_SN100_A = 0xa3, /**< NFCC SN100_A */
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NFCC_SN100_B = 0xa4, /**< NFCC SN100_B */
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NFCC_PN66T = 0x18, /**< NFCC PN66T */
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NFCC_NOT_SUPPORTED = 0xFF /**< NFCC is not supported */
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};
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#endif
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