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356 lines
8.4 KiB
356 lines
8.4 KiB
/* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CNSS_MAIN_H
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#define _CNSS_MAIN_H
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#include <linux/esoc_client.h>
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#include <linux/etherdevice.h>
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#include <linux/msm-bus.h>
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#include <linux/pm_qos.h>
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#include <linux/of.h>
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#include <net/cnss2.h>
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#include <soc/qcom/memory_dump.h>
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#include <soc/qcom/subsystem_restart.h>
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#include "qmi.h"
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#define MAX_NO_OF_MAC_ADDR 4
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#define QMI_WLFW_MAX_TIMESTAMP_LEN 32
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#define CNSS_RDDM_TIMEOUT_MS 20000
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#define RECOVERY_TIMEOUT 60000
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#define CNSS_EVENT_SYNC BIT(0)
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#define CNSS_EVENT_UNINTERRUPTIBLE BIT(1)
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#define CNSS_EVENT_SYNC_UNINTERRUPTIBLE (CNSS_EVENT_SYNC | \
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CNSS_EVENT_UNINTERRUPTIBLE)
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#define CNSS_FW_PATH_MAX_LEN 32
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#define CNSS_MAX_DEV_NUM 2
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enum cnss_dev_bus_type {
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CNSS_BUS_NONE = -1,
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CNSS_BUS_PCI,
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CNSS_BUS_USB,
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};
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struct cnss_vreg_cfg {
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const char *name;
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u32 min_uv;
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u32 max_uv;
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u32 load_ua;
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u32 delay_us;
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};
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struct cnss_vreg_info {
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struct list_head list;
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struct regulator *reg;
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struct cnss_vreg_cfg cfg;
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u32 enabled;
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};
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struct cnss_pinctrl_info {
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struct pinctrl *pinctrl;
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struct pinctrl_state *bootstrap_active;
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struct pinctrl_state *wlan_en_active;
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struct pinctrl_state *wlan_en_sleep;
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u32 activated;
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};
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struct cnss_subsys_info {
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struct subsys_device *subsys_device;
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struct subsys_desc subsys_desc;
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void *subsys_handle;
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};
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struct cnss_ramdump_info {
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struct ramdump_device *ramdump_dev;
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unsigned long ramdump_size;
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void *ramdump_va;
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phys_addr_t ramdump_pa;
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struct msm_dump_data dump_data;
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};
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struct cnss_dump_seg {
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unsigned long address;
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void *v_address;
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unsigned long size;
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u32 type;
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};
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struct cnss_dump_data {
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u32 version;
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u32 magic;
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char name[32];
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phys_addr_t paddr;
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int nentries;
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u32 seg_version;
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};
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struct cnss_ramdump_info_v2 {
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struct ramdump_device *ramdump_dev;
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unsigned long ramdump_size;
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void *dump_data_vaddr;
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bool dump_data_valid;
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struct cnss_dump_data dump_data;
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};
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struct cnss_esoc_info {
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struct esoc_desc *esoc_desc;
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bool notify_modem_status;
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void *modem_notify_handler;
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int modem_current_status;
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};
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struct cnss_bus_bw_info {
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struct msm_bus_scale_pdata *bus_scale_table;
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u32 bus_client;
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int current_bw_vote;
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};
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struct cnss_fw_mem {
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size_t size;
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void *va;
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phys_addr_t pa;
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bool valid;
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u32 type;
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};
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struct wlfw_rf_chip_info {
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u32 chip_id;
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u32 chip_family;
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};
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struct wlfw_rf_board_info {
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u32 board_id;
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};
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struct wlfw_soc_info {
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u32 soc_id;
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};
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struct wlfw_fw_version_info {
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u32 fw_version;
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char fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN + 1];
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};
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enum cnss_mem_type {
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CNSS_MEM_TYPE_MSA,
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CNSS_MEM_TYPE_DDR,
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CNSS_MEM_BDF,
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CNSS_MEM_M3,
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CNSS_MEM_CAL_V01,
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CNSS_MEM_DPD_V01,
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};
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enum cnss_fw_dump_type {
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CNSS_FW_IMAGE,
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CNSS_FW_RDDM,
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CNSS_FW_REMOTE_HEAP,
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};
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enum cnss_driver_event_type {
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CNSS_DRIVER_EVENT_SERVER_ARRIVE,
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CNSS_DRIVER_EVENT_SERVER_EXIT,
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CNSS_DRIVER_EVENT_REQUEST_MEM,
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CNSS_DRIVER_EVENT_FW_MEM_READY,
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CNSS_DRIVER_EVENT_FW_READY,
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CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
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CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
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CNSS_DRIVER_EVENT_REGISTER_DRIVER,
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CNSS_DRIVER_EVENT_UNREGISTER_DRIVER,
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CNSS_DRIVER_EVENT_RECOVERY,
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CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
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CNSS_DRIVER_EVENT_POWER_UP,
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CNSS_DRIVER_EVENT_POWER_DOWN,
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CNSS_DRIVER_EVENT_IDLE_RESTART,
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CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
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CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
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CNSS_DRIVER_EVENT_QDSS_TRACE_SAVE,
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CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
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CNSS_DRIVER_EVENT_CAL_UPDATE,
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CNSS_DRIVER_EVENT_CAL_DOWNLOAD,
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CNSS_DRIVER_EVENT_MAX,
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};
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enum cnss_driver_state {
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CNSS_QMI_WLFW_CONNECTED,
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CNSS_FW_MEM_READY,
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CNSS_FW_READY,
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CNSS_COLD_BOOT_CAL,
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CNSS_DRIVER_LOADING,
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CNSS_DRIVER_UNLOADING,
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CNSS_DRIVER_IDLE_RESTART,
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CNSS_DRIVER_IDLE_SHUTDOWN,
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CNSS_DRIVER_PROBED,
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CNSS_DRIVER_RECOVERY,
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CNSS_FW_BOOT_RECOVERY,
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CNSS_DEV_ERR_NOTIFY,
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CNSS_DRIVER_DEBUG,
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CNSS_IN_SUSPEND_RESUME,
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};
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struct cnss_recovery_data {
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enum cnss_recovery_reason reason;
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};
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enum cnss_pins {
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CNSS_WLAN_EN,
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CNSS_PCIE_TXP,
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CNSS_PCIE_TXN,
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CNSS_PCIE_RXP,
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CNSS_PCIE_RXN,
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CNSS_PCIE_REFCLKP,
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CNSS_PCIE_REFCLKN,
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CNSS_PCIE_RST,
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CNSS_PCIE_WAKE,
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};
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struct cnss_pin_connect_result {
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u32 fw_pwr_pin_result;
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u32 fw_phy_io_pin_result;
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u32 fw_rf_pin_result;
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u32 host_pin_result;
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};
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enum cnss_debug_quirks {
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LINK_DOWN_SELF_RECOVERY,
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SKIP_DEVICE_BOOT,
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USE_CORE_ONLY_FW,
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SKIP_RECOVERY,
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QMI_BYPASS,
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ENABLE_WALTEST,
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ENABLE_PCI_LINK_DOWN_PANIC,
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FBC_BYPASS,
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ENABLE_DAEMON_SUPPORT,
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IGNORE_PCI_LINK_FAILURE,
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};
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enum cnss_bdf_type {
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CNSS_BDF_BIN,
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CNSS_BDF_ELF,
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CNSS_BDF_REGDB = 4,
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CNSS_BDF_DUMMY = 255,
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};
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struct cnss_control_params {
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unsigned long quirks;
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unsigned int mhi_timeout;
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unsigned int qmi_timeout;
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unsigned int bdf_type;
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};
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enum cnss_ce_index {
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CNSS_CE_00,
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CNSS_CE_01,
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CNSS_CE_02,
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CNSS_CE_03,
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CNSS_CE_04,
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CNSS_CE_05,
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CNSS_CE_06,
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CNSS_CE_07,
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CNSS_CE_08,
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CNSS_CE_09,
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CNSS_CE_10,
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CNSS_CE_11,
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CNSS_CE_COMMON,
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};
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struct cnss_plat_data {
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struct platform_device *plat_dev;
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enum cnss_driver_mode driver_mode;
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void *bus_priv;
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enum cnss_dev_bus_type bus_type;
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struct list_head vreg_list;
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struct cnss_pinctrl_info pinctrl_info;
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struct cnss_subsys_info subsys_info;
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struct cnss_ramdump_info ramdump_info;
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struct cnss_ramdump_info_v2 ramdump_info_v2;
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struct cnss_esoc_info esoc_info;
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struct cnss_bus_bw_info bus_bw_info;
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struct notifier_block modem_nb;
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struct cnss_platform_cap cap;
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struct pm_qos_request qos_request;
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struct cnss_device_version device_version;
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unsigned long device_id;
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enum cnss_driver_status driver_status;
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u32 recovery_count;
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unsigned long driver_state;
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struct list_head event_list;
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spinlock_t event_lock; /* spinlock for driver work event handling */
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struct work_struct event_work;
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struct workqueue_struct *event_wq;
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struct qmi_handle qmi_wlfw;
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struct wlfw_rf_chip_info chip_info;
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struct wlfw_rf_board_info board_info;
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struct wlfw_soc_info soc_info;
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struct wlfw_fw_version_info fw_version_info;
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u32 fw_mem_seg_len;
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struct cnss_fw_mem fw_mem[QMI_WLFW_MAX_NUM_MEM_SEG_V01];
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struct cnss_fw_mem m3_mem;
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u32 qdss_mem_seg_len;
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struct cnss_fw_mem qdss_mem[QMI_WLFW_MAX_NUM_MEM_SEG_V01];
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u32 *qdss_reg;
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struct cnss_pin_connect_result pin_result;
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struct dentry *root_dentry;
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atomic_t pm_count;
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struct timer_list fw_boot_timer;
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struct completion power_up_complete;
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struct completion cal_complete;
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struct mutex dev_lock; /* mutex for register access through debugfs */
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u32 diag_reg_read_addr;
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u32 diag_reg_read_mem_type;
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u32 diag_reg_read_len;
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u8 *diag_reg_read_buf;
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bool cal_done;
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char firmware_name[CNSS_FW_PATH_MAX_LEN];
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struct completion rddm_complete;
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struct completion recovery_complete;
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struct cnss_control_params ctrl_params;
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u32 is_converged_dt;
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struct device_node *dev_node;
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u8 set_wlaon_pwr_ctrl;
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bool fw_pcie_gen_switch;
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u8 pcie_gen_speed;
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u32 rc_num;
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char device_name[16];
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u32 idx;
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bool enumerate_done;
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int qrtr_node_id;
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unsigned int wlfw_service_instance_id;
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};
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struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev);
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struct cnss_plat_data *cnss_get_plat_priv_by_rc_num(int rc_num);
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int cnss_get_plat_env_count(void);
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struct cnss_plat_data *cnss_get_plat_env(int index);
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bool cnss_get_dual_wlan(void);
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int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
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enum cnss_driver_event_type type,
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u32 flags, void *data);
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int cnss_get_vreg(struct cnss_plat_data *plat_priv);
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int cnss_get_pinctrl(struct cnss_plat_data *plat_priv);
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void cnss_put_vreg(struct cnss_plat_data *plat_priv);
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void cnss_put_pinctrl(struct cnss_plat_data *plat_priv);
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int cnss_power_on_device(struct cnss_plat_data *plat_priv);
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void cnss_power_off_device(struct cnss_plat_data *plat_priv);
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int cnss_register_subsys(struct cnss_plat_data *plat_priv);
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void cnss_unregister_subsys(struct cnss_plat_data *plat_priv);
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int cnss_register_ramdump(struct cnss_plat_data *plat_priv);
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void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv);
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void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv);
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const char *cnss_get_fw_path(struct cnss_plat_data *plat_priv);
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int cnss_dev_specific_power_on(struct cnss_plat_data *plat_priv);
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#endif /* _CNSS_MAIN_H */
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